riscv/sifive-blocks
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gpio: Use Synchronizer for the inputs

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This commit is contained in:
Megan Wachs 2017-09-05 18:35:09 -07:00
parent 1feaefe4c5
commit 48222bcd2d
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/devices/gpio/GPIO.scala
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@ -4,6 +4,7 @@ package sifive.blocks.devices.gpio
import Chisel._ import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.regmapper._ import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle} import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
@ -106,7 +107,7 @@ trait HasGPIOModuleContents extends Module with HasRegMap {
// Synchronize Input to get valueReg // Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width)) val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
val inSyncReg = ShiftRegister(inVal, 3) val inSyncReg = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg) val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration // Interrupt Configuration