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LazyModule: provide Parameters

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This tracks PR #478 in rocketchip.
This commit is contained in:
Wesley W. Terpstra
2016-12-07 13:21:20 -08:00
parent 1443834186
commit 45c491cd69
7 changed files with 27 additions and 27 deletions
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12
src/main/scala/devices/uart/UART.scala
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@ -46,9 +46,9 @@ class UARTPortIO extends Bundle {
}
trait MixUARTParameters {
val params: (UARTConfig, Parameters)
val c = params._1
implicit val p = params._2
implicit val p: Parameters
val params: UARTConfig
val c = params
}
trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
@ -269,7 +269,7 @@ class Majority(in: Set[Bool]) {
}
// Magic TL2 Incantation to create a TL2 Slave
class UART(c: UARTConfig)(implicit val p: Parameters)
class UART(c: UARTConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle((c, p), _) with UARTTopBundle)(
new TLRegModule((c, p), _, _) with UARTTopModule)
new TLRegBundle(c, _) with UARTTopBundle)(
new TLRegModule(c, _, _) with UARTTopModule)