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LazyModule: provide Parameters

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This tracks PR #478 in rocketchip.
This commit is contained in:
Wesley W. Terpstra
2016-12-07 13:21:20 -08:00
parent 1443834186
commit 45c491cd69
7 changed files with 27 additions and 27 deletions
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12
src/main/scala/devices/gpio/GPIO.scala
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@ -11,9 +11,9 @@ import util.AsyncResetRegVec
case class GPIOConfig(address: BigInt, width: Int)
trait HasGPIOParameters {
val params: Tuple2[Parameters, GPIOConfig]
implicit val p = params._1
val c = params._2
implicit val p: Parameters
val params: GPIOConfig
val c = params
}
// YAGNI: Make the PUE, DS, and
@ -289,7 +289,7 @@ object GPIOInputPinCtrl {
}
// Magic TL2 Incantation to create a TL2 Slave
class TLGPIO(p: Parameters, c: GPIOConfig)
class TLGPIO(c: GPIOConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(Tuple2(p, c), _) with GPIOBundle)(
new TLRegModule(Tuple2(p, c), _, _) with GPIOModule)
new TLRegBundle(c, _) with GPIOBundle)(
new TLRegModule(c, _, _) with GPIOModule)

2
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -8,7 +8,7 @@ import uncore.tilelink2.TLFragmenter
trait PeripheryGPIO {
this: TopNetwork { val gpioConfig: GPIOConfig } =>
val gpio = LazyModule(new TLGPIO(p, gpioConfig))
val gpio = LazyModule(new TLGPIO(gpioConfig))
gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := gpio.intnode
}