riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

i2c/uart: Name the synchronizers

Browse Source
This commit is contained in:
Megan Wachs
2017-09-05 18:40:22 -07:00
parent 48222bcd2d
commit 4381e395af
2 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/i2c/I2CPins.scala
View File

@@ -18,11 +18,13 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true))
i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true),
name = Some("i2c_scl_sync"))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true))
i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true),
name = Some("i2c_sda_sync"))
}
}
}

2
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
}
}
}