From a814cba04ffc83b0715339ee650eac358d7852b8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 19 Aug 2017 12:36:28 -0700 Subject: [PATCH 1/2] spi: put a request buffer infront of SPI This will prevent SPI from blocking other pbus requests. --- src/main/scala/devices/spi/SPIPeriphery.scala | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 8097894..6e58647 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -4,8 +4,8 @@ package sifive.blocks.devices.spi import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} -import freechips.rocketchip.tilelink.{TLFragmenter} +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams} +import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer} import freechips.rocketchip.util.HeterogeneousBag case object PeripherySPIKey extends Field[Seq[SPIParams]] @@ -41,7 +41,10 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus { val qspis = spiFlashParams map { params => val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params)) qspi.rnode := pbus.toVariableWidthSlaves - qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves) + qspi.fnode := + TLFragmenter(1, pbus.blockBytes)( + TLBuffer(BufferParams(8), BufferParams.none)( + pbus.toFixedWidthSlaves)) ibus.fromSync := qspi.intnode qspi } From 70c25846b8290376fd3851cb896d2eb91f2bb5b1 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sun, 20 Aug 2017 12:39:38 -0700 Subject: [PATCH 2/2] spi: Make memory mapped interface depth a parameter --- src/main/scala/devices/spi/SPIPeriphery.scala | 2 +- src/main/scala/devices/spi/TLSPIFlash.scala | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 6e58647..595ffc3 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -43,7 +43,7 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus { qspi.rnode := pbus.toVariableWidthSlaves qspi.fnode := TLFragmenter(1, pbus.blockBytes)( - TLBuffer(BufferParams(8), BufferParams.none)( + TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)( pbus.toFixedWidthSlaves)) ibus.fromSync := qspi.intnode qspi diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index bfec1d1..e433fec 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.util.HeterogeneousBag trait SPIFlashParamsBase extends SPIParamsBase { val fAddress: BigInt val fSize: BigInt + val fBufferDepth: Int val insnAddrBytes: Int val insnPadLenBits: Int @@ -22,6 +23,7 @@ trait SPIFlashParamsBase extends SPIParamsBase { case class SPIFlashParams( rAddress: BigInt, fAddress: BigInt, + fBufferDepth: Int = 0, rSize: BigInt = 0x1000, fSize: BigInt = 0x20000000, rxDepth: Int = 8,