diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 8097894..595ffc3 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -4,8 +4,8 @@ package sifive.blocks.devices.spi import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} -import freechips.rocketchip.tilelink.{TLFragmenter} +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams} +import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer} import freechips.rocketchip.util.HeterogeneousBag case object PeripherySPIKey extends Field[Seq[SPIParams]] @@ -41,7 +41,10 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus { val qspis = spiFlashParams map { params => val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params)) qspi.rnode := pbus.toVariableWidthSlaves - qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves) + qspi.fnode := + TLFragmenter(1, pbus.blockBytes)( + TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)( + pbus.toFixedWidthSlaves)) ibus.fromSync := qspi.intnode qspi } diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala index bfec1d1..e433fec 100644 --- a/src/main/scala/devices/spi/TLSPIFlash.scala +++ b/src/main/scala/devices/spi/TLSPIFlash.scala @@ -11,6 +11,7 @@ import freechips.rocketchip.util.HeterogeneousBag trait SPIFlashParamsBase extends SPIParamsBase { val fAddress: BigInt val fSize: BigInt + val fBufferDepth: Int val insnAddrBytes: Int val insnPadLenBits: Int @@ -22,6 +23,7 @@ trait SPIFlashParamsBase extends SPIParamsBase { case class SPIFlashParams( rAddress: BigInt, fAddress: BigInt, + fBufferDepth: Int = 0, rSize: BigInt = 0x1000, fSize: BigInt = 0x20000000, rxDepth: Int = 8,