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diplomacy: add reg-names to devices (#22)

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Wesley W. Terpstra 2017-06-28 17:45:18 -07:00 committed by GitHub
parent 2154e9eb3f
commit 3d8c502fce
2 changed files with 4 additions and 4 deletions
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2
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters( slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg, resources = device.reg("mem"),
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = true, executable = true,
supportsWrite = TransferSizes(1, 256*8), supportsWrite = TransferSizes(1, 256*8),

6
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@ -181,8 +181,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
"device_type" -> Seq(ResourceString("pci")), "device_type" -> Seq(ResourceString("pci")),
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) => "ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, perms)) =>
ResourceMapping(address, BigInt(0x02000000) << 64) }, ResourceMapping(address, BigInt(0x02000000) << 64, perms) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil, "interrupt-controller" -> Nil,
"#address-cells" -> ofInt(0), "#address-cells" -> ofInt(0),
@ -203,7 +203,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters( slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)), address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg, resources = device.reg("control"),
supportsWrite = TransferSizes(1, 4), supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4), supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // AXI4-Lite never interleaves responses interleavedId = Some(0))), // AXI4-Lite never interleaves responses