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device pins: Create classes that can be something other than a Pin subclass

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This commit is contained in:
Megan Wachs 2017-09-20 16:43:42 -07:00
parent 6a13639cf3
commit 38f537c438
4 changed files with 47 additions and 21 deletions
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7
src/main/scala/devices/i2c/I2CPins.scala
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@ -6,13 +6,18 @@ import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
class I2CPins[T <: Pin](pingen: () => T) extends Bundle { class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
val scl: T = pingen() val scl: T = pingen()
val sda: T = pingen() val sda: T = pingen()
override def cloneType: this.type = override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
}
class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen) {
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
withClockAndReset(clock, reset) { withClockAndReset(clock, reset) {

9
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -13,10 +13,17 @@ class PWMPortIO(val c: PWMParams) extends Bundle {
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type] override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
} }
class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle { class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
val pwm: Vec[T] = Vec(c.ncmp, pingen()) val pwm: Vec[T] = Vec(c.ncmp, pingen())
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
}
class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) {
override def cloneType: this.type = override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]

19
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -4,10 +4,8 @@ package sifive.blocks.devices.uart
import Chisel._ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus} import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
case object PeripheryUARTKey extends Field[Seq[UARTParams]] case object PeripheryUARTKey extends Field[Seq[UARTParams]]
@ -39,20 +37,3 @@ trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUA
io <> device.module.io.port io <> device.module.io.port
} }
} }
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
val rxd = pingen()
val txd = pingen()
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
}
}
}

33
src/main/scala/devices/uart/UARTPins.scala Normal file
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@ -0,0 +1,33 @@
// See LICENSE for license details.
package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
val rxd = pingen()
val txd = pingen()
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
}
class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen, c) {
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
}
}
}