From c1872c574b1e471778ec28e6a782b6547e6917da Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 21 Mar 2017 22:12:37 -0700 Subject: [PATCH] update TLRegisterNode to take Seq of AddressSet --- src/main/scala/devices/spi/TLSPI.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala index b20b524..5c5b9bf 100644 --- a/src/main/scala/devices/spi/TLSPI.scala +++ b/src/main/scala/devices/spi/TLSPI.scala @@ -110,7 +110,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule { require(isPow2(c.rSize)) val device = new SimpleDevice("spi", Seq("sifive,spi0")) - val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w) + val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w) val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) }