riscv/sifive-blocks
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Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

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This commit is contained in:
Megan Wachs 2017-07-25 07:05:22 -07:00
commit 2139ab0d98
2 changed files with 8 additions and 7 deletions
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8
src/main/scala/devices/uart/UART.scala
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@ -3,8 +3,6 @@ package sifive.blocks.devices.uart
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.RTCPeriod
import freechips.rocketchip.diplomacy.DTSTimebase
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
@ -15,6 +13,7 @@ case class UARTParams(
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
divisorInit: Int = 0,
divisorBits: Int = 16,
oversample: Int = 4,
nSamples: Int = 3,
@ -25,6 +24,7 @@ trait HasUARTParameters {
def c: UARTParams
def uartDataBits = c.dataBits
def uartStopBits = c.stopBits
def uartDivisorInit = c.divisorInit
def uartDivisorBits = c.divisorBits
def uartOversample = c.oversample
@ -34,6 +34,7 @@ trait HasUARTParameters {
def uartNTxEntries = c.nTxEntries
def uartNRxEntries = c.nRxEntries
require(uartDivisorInit != 0) // should have been initialized during instantiation
require(uartDivisorBits > uartOversample)
require(uartOversampleFactor > uartNSamples)
}
@ -205,8 +206,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits))
val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)
private val txCountBits = log2Floor(uartNTxEntries) + 1

7
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
import sifive.blocks.util.ShiftRegisterInit
@ -12,9 +12,10 @@ import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
val uartParams = p(PeripheryUARTKey)
val uartParams = p(PeripheryUARTKey)
val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params))
val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
uart.node := pbus.toVariableWidthSlaves
ibus.fromSync := uart.intnode
uart