Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
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commit
2139ab0d98
@ -3,8 +3,6 @@ package sifive.blocks.devices.uart
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import Chisel._
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex.RTCPeriod
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import freechips.rocketchip.diplomacy.DTSTimebase
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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@ -15,6 +13,7 @@ case class UARTParams(
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address: BigInt,
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address: BigInt,
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dataBits: Int = 8,
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dataBits: Int = 8,
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stopBits: Int = 2,
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stopBits: Int = 2,
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divisorInit: Int = 0,
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divisorBits: Int = 16,
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divisorBits: Int = 16,
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oversample: Int = 4,
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oversample: Int = 4,
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nSamples: Int = 3,
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nSamples: Int = 3,
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@ -25,6 +24,7 @@ trait HasUARTParameters {
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def c: UARTParams
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def c: UARTParams
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def uartDataBits = c.dataBits
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def uartDataBits = c.dataBits
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def uartStopBits = c.stopBits
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def uartStopBits = c.stopBits
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def uartDivisorInit = c.divisorInit
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def uartDivisorBits = c.divisorBits
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def uartDivisorBits = c.divisorBits
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def uartOversample = c.oversample
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def uartOversample = c.oversample
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@ -34,6 +34,7 @@ trait HasUARTParameters {
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def uartNTxEntries = c.nTxEntries
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def uartNTxEntries = c.nTxEntries
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def uartNRxEntries = c.nRxEntries
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def uartNRxEntries = c.nRxEntries
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require(uartDivisorInit != 0) // should have been initialized during instantiation
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require(uartDivisorBits > uartOversample)
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require(uartDivisorBits > uartOversample)
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require(uartOversampleFactor > uartNSamples)
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require(uartOversampleFactor > uartNSamples)
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}
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}
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@ -205,8 +206,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
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val rxm = Module(new UARTRx(params))
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val rxm = Module(new UARTRx(params))
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val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
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val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
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val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
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val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
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val div = Reg(init = UInt(divinit, uartDivisorBits))
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private val stopCountBits = log2Up(uartStopBits)
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private val stopCountBits = log2Up(uartStopBits)
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private val txCountBits = log2Floor(uartNTxEntries) + 1
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private val txCountBits = log2Floor(uartNTxEntries) + 1
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@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
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import Chisel._
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
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import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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import sifive.blocks.devices.pinctrl.{Pin}
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import sifive.blocks.devices.pinctrl.{Pin}
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import sifive.blocks.util.ShiftRegisterInit
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import sifive.blocks.util.ShiftRegisterInit
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@ -13,8 +13,9 @@ case object PeripheryUARTKey extends Field[Seq[UARTParams]]
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trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
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trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
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val uartParams = p(PeripheryUARTKey)
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val uartParams = p(PeripheryUARTKey)
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val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
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val uarts = uartParams map { params =>
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val uarts = uartParams map { params =>
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val uart = LazyModule(new TLUART(pbus.beatBytes, params))
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val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit)))
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uart.node := pbus.toVariableWidthSlaves
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uart.node := pbus.toVariableWidthSlaves
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ibus.fromSync := uart.intnode
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ibus.fromSync := uart.intnode
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uart
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uart
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