riscv/sifive-blocks
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Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD

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Megan Wachs
2017-03-30 20:01:30 -07:00
parent 3f6f10f4ed 6a3b5e1a31
commit 1af6ce1c85
1 changed files with 3 additions and 1 deletions
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src/main/scala/devices/spi/SPIArbiter.scala
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@@ -20,7 +20,9 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits)) io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt)) io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt)) io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
io.outer.cs := Mux1H(sel, io.inner.map(_.cs)) // Workaround for overzealous combinational loop detection
io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs)
require(n == 2, "SPIArbiter currently only supports 2 clients")
(io.inner zip sel).foreach { case (inner, s) => (io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s inner.tx.ready := io.outer.tx.ready && s