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xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)

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This commit is contained in:
Wesley W. Terpstra
2017-05-08 01:08:37 -07:00
committed by GitHub
parent 9cb80ac913
commit 178ac84b59
2 changed files with 5 additions and 6 deletions
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src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@@ -205,7 +205,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4))),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // AXI4-Lite never interleaves responses
beatBytes = 4)))
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(