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xilinxvc707pciex1: push to a dedicated clock domain

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This commit is contained in:
Wesley W. Terpstra 2017-05-12 22:59:48 -07:00
parent b3f9607512
commit 0ed21ba465
2 changed files with 20 additions and 11 deletions
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15
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -20,9 +20,9 @@ class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
} }
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLInputNode() val slave = TLAsyncInputNode()
val control = TLInputNode() val control = TLAsyncInputNode()
val master = TLOutputNode() val master = TLAsyncOutputNode()
val intnode = IntOutputNode() val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@ -33,21 +33,24 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))( AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)( AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8)( TLToAXI4(beatBytes=8)(
slave))))) TLAsyncCrossingSink()(
slave))))))
axi_to_pcie_x1.control := axi_to_pcie_x1.control :=
AXI4Buffer()( AXI4Buffer()(
AXI4UserYanker()( AXI4UserYanker()(
TLToAXI4(beatBytes=4)( TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))( TLFragmenter(4, p(coreplex.CacheBlockBytes))(
control)))) TLAsyncCrossingSink()(
control)))))
master := master :=
TLAsyncCrossingSource()(
TLWidthWidget(8)( TLWidthWidget(8)(
AXI4ToTL()( AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))( AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()( AXI4Fragmenter()(
axi_to_pcie_x1.master)))) axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode intnode := axi_to_pcie_x1.intnode

16
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -8,15 +8,18 @@ import rocketchip.{
HasTopLevelNetworksModule, HasTopLevelNetworksModule,
HasTopLevelNetworksBundle HasTopLevelNetworksBundle
} }
import uncore.tilelink2.TLWidthWidget import uncore.tilelink2._
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks { trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
fsb.node := xilinxvc707pcie.master private val intXing = LazyModule(new IntXing)
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
intBus.intnode := xilinxvc707pcie.intnode xilinxvc707pcie.slave := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
intBus.intnode := intXing.intnode
intXing.intnode := xilinxvc707pcie.intnode
} }
trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle { trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
@ -28,4 +31,7 @@ trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
val io: HasPeripheryXilinxVC707PCIeX1Bundle val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
} }