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vc707axi: track rocketchip API changes (#16)

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Wesley W. Terpstra 2017-06-02 15:56:18 -07:00 committed by GitHub
parent 0f8722f80c
commit 0ca609d324
1 changed files with 2 additions and 1 deletions
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src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@ -181,7 +181,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
"device_type" -> Seq(ResourceString("pci")), "device_type" -> Seq(ResourceString("pci")),
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) => "ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _, _)) =>
ResourceMapping(address, BigInt(0x02000000) << 64) }, ResourceMapping(address, BigInt(0x02000000) << 64) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil, "interrupt-controller" -> Nil,
@ -211,6 +211,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters( masters = Seq(AXI4MasterParameters(
name = "VC707 PCIe",
id = IdRange(0, 1), id = IdRange(0, 1),
aligned = false))))) aligned = false)))))