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Use HomogenousBag to handle lists of peripherals

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Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
This commit is contained in:
Megan Wachs
2017-02-16 17:52:24 -08:00
parent 348bbb97f4
commit 03be9aba67
4 changed files with 7 additions and 27 deletions
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10
src/main/scala/devices/pwm/PWM.scala
View File

@ -44,16 +44,6 @@ case class PWMConfig(
regBytes: Int = 4,
ncmp: Int = 4,
cmpWidth: Int = 16)
{
val bc = new PWMBundleConfig(ncmp)
}
case class PWMBundleConfig(
ncmp: Int)
{
def union(that: PWMBundleConfig): PWMBundleConfig =
PWMBundleConfig(scala.math.max(ncmp, that.ncmp))
}
trait HasPWMParameters {
implicit val p: Parameters

10
src/main/scala/devices/pwm/PWMPeriphery.scala
View File

@ -6,19 +6,20 @@ import config._
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
class PWMPortIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
class PWMPinsIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
@ -43,8 +44,7 @@ trait PeripheryPWMBundle {
val p: Parameters
val pwmConfigs: Seq[PWMConfig]
} =>
val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
val pwms = HeterogeneousBag(pwmConfigs.map(new PWMPortIO(_)(p)))
}
trait PeripheryPWMModule {