2016-11-29 13:08:44 +01:00
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// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707pciex1
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import Chisel._
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import diplomacy.LazyModule
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2017-01-30 20:33:30 +01:00
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import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
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2016-11-29 13:08:44 +01:00
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import uncore.tilelink2.TLWidthWidget
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2017-01-30 20:33:30 +01:00
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trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
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2016-11-29 13:08:44 +01:00
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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l2.node := xilinxvc707pcie.master
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xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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intBus.intnode := xilinxvc707pcie.intnode
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}
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2017-01-30 20:33:30 +01:00
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trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
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2016-11-29 13:08:44 +01:00
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val xilinxvc707pcie = new XilinxVC707PCIeX1IO
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}
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2017-01-30 20:33:30 +01:00
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trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
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2016-11-29 13:08:44 +01:00
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val outer: PeripheryXilinxVC707PCIeX1
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val io: PeripheryXilinxVC707PCIeX1Bundle
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io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
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}
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