bb3f514e8d
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits. This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
193 lines
7.0 KiB
Scala
193 lines
7.0 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import rocket._
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import rocket.Util._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule}
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import uncore.devices._
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import uncore.converters._
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import coreplex._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import scala.collection.immutable.HashMap
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config(
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topDefinitions = {
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val configString = new GlobalVariable[String]
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val globalAddrMap = new GlobalVariable[AddrMap]
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val nCoreplexExtClients = new GlobalVariable[Int]
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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case BuildCoreplex =>
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(p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
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case NExtTopInterrupts => 2
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// Note that PLIC asserts that this is > 0.
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NCoreplexExtClients => nCoreplexExtClients
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => configString
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTop(p))
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case _ => throw new CDEMatchError
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}
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}
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})
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
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class DefaultBufferlessConfig extends Config(
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new WithBufferlessBroadcastHub ++ new BaseConfig)
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case _ => throw new CDEMatchError
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}
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)
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
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class DefaultL2FPGAConfig extends Config(
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new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here) => pname match {
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case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here) => pname match {
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case ExtMemSize => Dump("MEM_SIZE", n)
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case _ => throw new CDEMatchError
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}
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)
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class WithAHB extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.AHB
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case NExtMMIOAHBChannels => 1
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})
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class WithTL extends Config(
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(pname, site, here) => pname match {
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case TMemoryChannels => BusType.TL
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case NExtMMIOTLChannels => 1
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})
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class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
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class DefaultFPGASmallConfig extends Config(new WithSmallCores ++ new DefaultFPGAConfig)
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class DefaultSmallConfig extends Config(new WithSmallCores ++ new BaseConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
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class DualBankConfig extends Config(
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualBankL2Config extends Config(
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new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
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class DualChannelL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
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class DualChannelDualBankConfig extends Config(
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new WithNMemoryChannels(2) ++
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new WithNBanksPerMemChannel(2) ++ new BaseConfig)
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class DualChannelDualBankL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
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new WithL2Cache ++ new BaseConfig)
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class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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class WithMIFDataBits(n: Int) extends Config(
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(pname, site, here) => pname match {
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case MIFDataBits => Dump("MIF_DATA_BITS", n)
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})
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class MIF128BitConfig extends Config(
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new WithMIFDataBits(128) ++ new BaseConfig)
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class MIF32BitConfig extends Config(
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new WithMIFDataBits(32) ++ new BaseConfig)
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class SmallL2Config extends Config(
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Capacity(256) ++ new DefaultL2Config)
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class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
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class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
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class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
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class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
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class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
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class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
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class DualCoreConfig extends Config(
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new WithNCores(2) ++ new WithL2Cache ++ new BaseConfig)
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class TinyConfig extends Config(
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new WithScratchpads ++
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new WithSmallCores ++ new WithRV32 ++
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new WithStatelessBridge ++ new BaseConfig)
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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}
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)
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