80 lines
2.9 KiB
Scala
80 lines
2.9 KiB
Scala
package uncore
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import Chisel._
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
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val dst = UInt(width = conf.idBits)
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}
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class PhysicalNetworkIO[T <: Data](dType: T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val header = new PhysicalHeader
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val payload = dType.clone
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override def clone = { new PhysicalNetworkIO(dType).asInstanceOf[this.type] }
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}
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Module
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class BasicCrossbarIO[T <: Data](dType: T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val in = Vec.fill(conf.nEndpoints){Decoupled(new PhysicalNetworkIO(dType))}.flip
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val out = Vec.fill(conf.nEndpoints){Decoupled(new PhysicalNetworkIO(dType))}
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}
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class BasicCrossbar[T <: Data](dType: T, count: Int = 1)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new BasicCrossbarIO(dType)
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val rdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints)(Bool()))
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.nEndpoints, count))
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(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
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arb.valid := in.valid && (in.bits.header.dst === UInt(i))
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arb.bits := in.bits
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rdy := arb.ready && (in.bits.header.dst === UInt(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until conf.nEndpoints) {
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io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
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}
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}
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case class LogicalNetworkConfiguration(idBits: Int, nMasters: Int, nClients: Int) {
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val nEndpoints = nMasters + nClients
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}
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abstract class LogicalNetwork[TileLinkType <: Bundle](implicit conf: LogicalNetworkConfiguration) extends Module
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class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
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val dst = UInt(width = conf.idBits)
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}
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class LogicalNetworkIO[T <: Data](dType: T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val header = new LogicalHeader
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val payload = dType.clone
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override def clone = { new LogicalNetworkIO(dType).asInstanceOf[this.type] }
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}
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object DecoupledLogicalNetworkIOWrapper {
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def apply[T <: Data](in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0))(implicit conf: LogicalNetworkConfiguration) = {
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val out = Decoupled(new LogicalNetworkIO(in.bits.clone)).asDirectionless
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out.valid := in.valid
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out.bits.payload := in.bits
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out.bits.header.dst := dst
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out.bits.header.src := src
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in.ready := out.ready
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out
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}
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}
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object DecoupledLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
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val out = Decoupled(in.bits.payload.clone).asDirectionless
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out.valid := in.valid
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out.bits := in.bits.payload
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in.ready := out.ready
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out
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}
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}
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