rocket-chip/src/main/scala at f943c5d6efc87bbda14bb6a1aec6f2ebf1165064 - rocket-chip - Tiband Gitea

riscv/rocket-chip

Files

T

History

Wesley W. Terpstra f943c5d6ef rocketchip: connect rtcTick to coreplex

2016-10-31 11:42:47 -07:00

..

coreplex: reattach clint interrupt

2016-10-31 11:42:47 -07:00

rocketchip: use TileLink2 interrupts

2016-10-31 11:42:47 -07:00

rocketchip: must create bundles within Module scope

2016-10-31 11:42:47 -07:00

rocketchip: all of the address map now comes from TL2

2016-10-31 11:42:44 -07:00

regmapper RegisterCrossing: safe AsyncQueues are overkill here

2016-10-14 18:28:31 -07:00

rocket scratchpad: support atomics

2016-10-31 11:42:47 -07:00

rocketchip: connect rtcTick to coreplex

2016-10-31 11:42:47 -07:00

Plic: skip reserved interrupt in interrupt map printout

2016-10-31 11:42:47 -07:00

diplomacy: print out bus widths on edges in agent graph

2016-10-31 11:42:47 -07:00

Fixed AsyncFifo with reset messaging

2016-10-25 16:45:08 -07:00