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rocket-chip/src/main
Megan Wachs f86489b59e
JTAG: Use sorted map for stability (#1073)
* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup
2017-10-31 15:33:41 -07:00
..
scala JTAG: Use sorted map for stability (#1073) 2017-10-31 15:33:41 -07:00