84 lines
2.9 KiB
Scala
84 lines
2.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.tilelink2
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import Chisel._
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import config._
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import diplomacy._
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import util._
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// Do not use this for synthesis! Only for simulation.
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class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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{
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val device = new MemoryDevice
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(address),
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resources = device.reg,
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regionType = RegionType.UNCACHED,
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executable = executable,
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes)))
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// We require the address range to include an entire beat (for the write mask)
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require ((address.mask & (beatBytes-1)) == beatBytes-1)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
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if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
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val mask = bigBits(address.mask >> log2Ceil(beatBytes))
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val in = io.in(0)
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val edge = node.edgesIn(0)
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val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
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val memAddress = Cat(addrBits.reverse)
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val mem = Mem(1 << addrBits.size, Vec(beatBytes, Bits(width = 8)))
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// "Flow control"
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in.a.ready := in.d.ready
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in.d.valid := in.a.valid
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val hasData = edge.hasData(in.a.bits)
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val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
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in.d.bits := edge.AccessAck(in.a.bits, UInt(0))
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in.d.bits.data := Cat(mem(memAddress).reverse)
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in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
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when (in.a.fire() && hasData) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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/** Synthesizeable unit testing */
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import unittest._
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class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("ZeroDelay"))
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val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
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model.node := fuzz.node
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ram.node := TLDelayer(0.25)(model.node)
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class TLRAMZeroDelayTest(ramBeatBytes: Int, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes)).module).io.finished
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}
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