492 lines
22 KiB
Scala
492 lines
22 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.diplomacy
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.util.HeterogeneousBag
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import scala.collection.mutable.ListBuffer
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// DI = Downwards flowing Parameters received on the inner side of the node
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// UI = Upwards flowing Parameters generated by the inner side of the node
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// EI = Edge Parameters describing a connection on the inner side of the node
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// BI = Bundle type used when connecting to the inner side of the node
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trait InwardNodeImp[DI, UI, EI, BI <: Data]
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{
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def edgeI(pd: DI, pu: UI): EI
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def bundleI(ei: EI): BI
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def colour: String
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def reverse: Boolean = false
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def connect(edges: () => Seq[EI], bundles: () => Seq[(BI, BI)], enableMonitoring: Boolean)
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(implicit p: Parameters, sourceInfo: SourceInfo): (Option[MonitorBase], () => Unit) = {
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(None, () => bundles().foreach { case (i, o) => i <> o })
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}
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// optional methods to track node graph
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def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu // insert node into parameters
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def getO(pu: UI): Option[BaseNode] = None // most-outward common node
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def labelI(ei: EI) = ""
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}
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// DO = Downwards flowing Parameters generated by the outer side of the node
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// UO = Upwards flowing Parameters received on the outer side of the node
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// EO = Edge Parameters describing a connection on the outer side of the node
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// BO = Bundle type used when connecting to the outer side of the node
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trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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{
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def edgeO(pd: DO, pu: UO): EO
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def bundleO(eo: EO): BO
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// optional methods to track node graph
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def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd // insert node into parameters
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def getI(pd: DO): Option[BaseNode] = None // most-inward common node
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def labelO(eo: EO) = ""
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}
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class BaseNode
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{
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require (!LazyModule.stack.isEmpty, "You cannot create a node outside a LazyModule!")
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val lazyModule = LazyModule.stack.head
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val index = lazyModule.nodes.size
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lazyModule.nodes = this :: lazyModule.nodes
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val externalIn: Boolean
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val externalOut: Boolean
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def nodename = getClass.getName.split('.').last
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def name = lazyModule.name + "." + nodename
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def omitGraphML = outputs.isEmpty && inputs.isEmpty
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lazy val nodedebugstring: String = ""
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protected[diplomacy] def gci: Option[BaseNode] // greatest common inner
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protected[diplomacy] def gco: Option[BaseNode] // greatest common outer
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protected[diplomacy] def outputs: Seq[(BaseNode, String)]
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protected[diplomacy] def inputs: Seq[(BaseNode, String)]
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protected[diplomacy] def colour: String
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protected[diplomacy] def reverse: Boolean
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}
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case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
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(inward: InwardNode[DI, UI, BI], outward: OutwardNode[DO, UO, BO])
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extends Object with InwardNodeHandle[DI, UI, BI] with OutwardNodeHandle[DO, UO, BO]
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trait InwardNodeHandle[DI, UI, BI <: Data]
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{
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val inward: InwardNode[DI, UI, BI]
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def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] =
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inward.:=(h)(p, sourceInfo)
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def :*= (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] =
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inward.:*=(h)(p, sourceInfo)
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def :=* (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] =
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inward.:=*(h)(p, sourceInfo)
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}
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sealed trait NodeBinding
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case object BIND_ONCE extends NodeBinding
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case object BIND_QUERY extends NodeBinding
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case object BIND_STAR extends NodeBinding
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trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, UI, BI]
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{
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val inward = this
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protected[diplomacy] val numPI: Range.Inclusive
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI], NodeBinding)]()
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private var iRealized = false
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protected[diplomacy] def iPushed = accPI.size
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protected[diplomacy] def iPush(index: Int, node: OutwardNode[DI, UI, BI], binding: NodeBinding)(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (!noIs, s"${name}${lazyModule.line} was incorrectly connected as a sink" + info)
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require (!iRealized, s"${name}${lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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accPI += ((index, node, binding))
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}
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protected[diplomacy] lazy val iBindings = { iRealized = true; accPI.result() }
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protected[diplomacy] val iStar: Int
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protected[diplomacy] val iPortMapping: Seq[(Int, Int)]
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protected[diplomacy] val iParams: Seq[UI]
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val bundleIn: HeterogeneousBag[BI]
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}
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trait OutwardNodeHandle[DO, UO, BO <: Data]
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{
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val outward: OutwardNode[DO, UO, BO]
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}
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trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO, UO, BO]
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{
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val outward = this
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protected[diplomacy] val numPO: Range.Inclusive
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO], NodeBinding)]()
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private var oRealized = false
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protected[diplomacy] def oPushed = accPO.size
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protected[diplomacy] def oPush(index: Int, node: InwardNode [DO, UO, BO], binding: NodeBinding)(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noOs = numPO.size == 1 && numPO.contains(0)
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require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
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require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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accPO += ((index, node, binding))
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}
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protected[diplomacy] lazy val oBindings = { oRealized = true; accPO.result() }
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protected[diplomacy] val oStar: Int
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protected[diplomacy] val oPortMapping: Seq[(Int, Int)]
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protected[diplomacy] val oParams: Seq[DO]
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val bundleOut: HeterogeneousBag[BO]
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}
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abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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protected[diplomacy] val numPO: Range.Inclusive,
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protected[diplomacy] val numPI: Range.Inclusive)
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extends BaseNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
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protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
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protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
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protected[diplomacy] lazy val (oPortMapping, iPortMapping, oStar, iStar) = {
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val oStars = oBindings.filter { case (_,_,b) => b == BIND_STAR }.size
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val iStars = iBindings.filter { case (_,_,b) => b == BIND_STAR }.size
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val oKnown = oBindings.map { case (_, n, b) => b match {
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case BIND_ONCE => 1
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case BIND_QUERY => n.iStar
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case BIND_STAR => 0 }}.foldLeft(0)(_+_)
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val iKnown = iBindings.map { case (_, n, b) => b match {
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case BIND_ONCE => 1
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case BIND_QUERY => n.oStar
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case BIND_STAR => 0 }}.foldLeft(0)(_+_)
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val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
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val oSum = oBindings.map { case (_, n, b) => b match {
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case BIND_ONCE => 1
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case BIND_QUERY => n.iStar
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case BIND_STAR => oStar }}.scanLeft(0)(_+_)
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val iSum = iBindings.map { case (_, n, b) => b match {
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case BIND_ONCE => 1
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case BIND_QUERY => n.oStar
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case BIND_STAR => iStar }}.scanLeft(0)(_+_)
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val oTotal = oSum.lastOption.getOrElse(0)
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val iTotal = iSum.lastOption.getOrElse(0)
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require(numPO.contains(oTotal), s"${name} has ${oTotal} outputs, expected ${numPO}${lazyModule.line}")
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require(numPI.contains(iTotal), s"${name} has ${iTotal} inputs, expected ${numPI}${lazyModule.line}")
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(oSum.init zip oSum.tail, iSum.init zip iSum.tail, oStar, iStar)
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}
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lazy val oPorts = oBindings.flatMap { case (i, n, _) =>
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val (start, end) = n.iPortMapping(i)
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(start until end) map { j => (j, n) }
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}
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lazy val iPorts = iBindings.flatMap { case (i, n, _) =>
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val (start, end) = n.oPortMapping(i)
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(start until end) map { j => (j, n) }
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}
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protected[diplomacy] lazy val oParams: Seq[DO] = {
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val o = mapParamsD(oPorts.size, iPorts.map { case (i, n) => n.oParams(i) })
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require (o.size == oPorts.size, s"Bug in diplomacy; ${name} has ${o.size} != ${oPorts.size} down/up outer parameters${lazyModule.line}")
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o.map(outer.mixO(_, this))
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}
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protected[diplomacy] lazy val iParams: Seq[UI] = {
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val i = mapParamsU(iPorts.size, oPorts.map { case (o, n) => n.iParams(o) })
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require (i.size == iPorts.size, s"Bug in diplomacy; ${name} has ${i.size} != ${iPorts.size} up/down inner parameters${lazyModule.line}")
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i.map(inner.mixI(_, this))
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}
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protected[diplomacy] def gco = if (iParams.size != 1) None else inner.getO(iParams(0))
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protected[diplomacy] def gci = if (oParams.size != 1) None else outer.getI(oParams(0))
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => outer.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => inner.edgeI(n.oParams(o), i) }
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lazy val externalEdgesOut = if (externalOut) {edgesOut} else { Seq() }
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lazy val externalEdgesIn = if (externalIn) {edgesIn} else { Seq() }
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val flip = false // needed for blind nodes
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private def flipO(b: HeterogeneousBag[BO]) = if (flip) b.flip else b
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private def flipI(b: HeterogeneousBag[BI]) = if (flip) b else b.flip
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val wire = false // needed if you want to grab access to from inside a module
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private def wireO(b: HeterogeneousBag[BO]) = if (wire) Wire(b) else b
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private def wireI(b: HeterogeneousBag[BI]) = if (wire) Wire(b) else b
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lazy val bundleOut = wireO(flipO(HeterogeneousBag(edgesOut.map(outer.bundleO(_)))))
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lazy val bundleIn = wireI(flipI(HeterogeneousBag(edgesIn .map(inner.bundleI(_)))))
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// connects the outward part of a node with the inward part of this node
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private def bind(h: OutwardNodeHandle[DI, UI, BI], binding: NodeBinding, enableMonitoring: Boolean)
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(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = {
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val x = this // x := y
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val y = h.outward
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val info = sourceLine(sourceInfo, " at ", "")
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require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
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val i = x.iPushed
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val o = y.oPushed
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y.oPush(i, x, binding match {
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case BIND_ONCE => BIND_ONCE
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case BIND_STAR => BIND_QUERY
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case BIND_QUERY => BIND_STAR })
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x.iPush(o, y, binding)
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def edges() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j => x.edgesIn(iStart+j) }
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}
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def bundles() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j =>
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(x.bundleIn(iStart+j), y.bundleOut(oStart+j))
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}
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}
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val (out, newbinding) = inner.connect(edges _, bundles _, enableMonitoring)
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LazyModule.stack.head.bindings = newbinding :: LazyModule.stack.head.bindings
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out
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}
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override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_ONCE, true)
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override def :*= (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_STAR, true)
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override def :=* (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_QUERY, true)
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def connectButDontMonitor(h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_ONCE, false)
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def connectButDontMonitorSlaves(h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_STAR, false)
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def connectButDontMonitorMasters(h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[MonitorBase] = bind(h, BIND_QUERY, false)
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// meta-data for printing the node graph
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protected[diplomacy] def colour = inner.colour
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protected[diplomacy] def reverse = inner.reverse
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protected[diplomacy] def outputs = oPorts.map(_._2) zip edgesOut.map(e => outer.labelO(e))
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protected[diplomacy] def inputs = iPorts.map(_._2) zip edgesIn .map(e => inner.labelI(e))
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}
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abstract class MixedCustomNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int)
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def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
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def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
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}
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abstract class CustomNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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extends MixedCustomNode(imp, imp)(numPO, numPI)
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class MixedAdapterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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dFn: DI => DO,
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uFn: UO => UI,
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num: Range.Inclusive = 0 to 999)
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extends MixedNode(inner, outer)(num, num)
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{
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val externalIn: Boolean = true
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val externalOut: Boolean = true
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (oStars + iStars <= 1, s"${name} (an adapter) appears left of a :*= ${iStars} times and right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
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if (oStars > 0) {
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require (iKnown >= oKnown, s"${name} (an adapter) has ${oKnown} outputs and ${iKnown} inputs; cannot assign ${iKnown-oKnown} edges to resolve :=*${lazyModule.line}")
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(0, iKnown - oKnown)
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} else {
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require (oKnown >= iKnown, s"${name} (an adapter) has ${oKnown} outputs and ${iKnown} inputs; cannot assign ${oKnown-iKnown} edges to resolve :*=${lazyModule.line}")
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(oKnown - iKnown, 0)
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}
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}
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protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] = {
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require(n == p.size, s"${name} has ${p.size} inputs and ${n} outputs; they must match${lazyModule.line}")
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p.map(dFn)
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}
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protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] = {
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require(n == p.size, s"${name} has ${n} inputs and ${p.size} outputs; they must match${lazyModule.line}")
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p.map(uFn)
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}
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}
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class MixedNexusNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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dFn: Seq[DI] => DO,
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uFn: Seq[UO] => UI,
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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// require (numPO.end >= 1, s"${name} does not accept outputs${lazyModule.line}")
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// require (numPI.end >= 1, s"${name} does not accept inputs${lazyModule.line}")
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val externalIn: Boolean = true
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val externalOut: Boolean = true
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (iStars == 0, s"${name} (a nexus) appears left of :*= (perhaps you should flip the '*' to :=*?)${lazyModule.line}")
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require (oStars == 0, s"${name} (a nexus) appears right of a :=* (perhaps you should flip the '*' to :*=?)${lazyModule.line}")
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(0, 0)
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}
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protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] = { val a = dFn(p); Seq.fill(n)(a) }
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protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] = { val a = uFn(p); Seq.fill(n)(a) }
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}
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class AdapterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: D => D,
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uFn: U => U,
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num: Range.Inclusive = 0 to 999)
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extends MixedAdapterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, num)
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class NexusNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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dFn: Seq[D] => D,
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uFn: Seq[U] => U,
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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extends MixedNexusNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI)
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case class SplitterArg[T](newSize: Int, ports: Seq[T])
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class MixedSplitterNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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dFn: SplitterArg[DI] => Seq[DO],
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uFn: SplitterArg[UO] => Seq[UI],
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numPO: Range.Inclusive = 1 to 999,
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numPI: Range.Inclusive = 1 to 999)
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extends MixedNode(inner, outer)(numPO, numPI)
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{
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override val externalIn: Boolean = true
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override val externalOut: Boolean = true
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|
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protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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|
require (oKnown == 0, s"${name} (a splitter) appears right of a := or :*=; use a :=* instead${lazyModule.line}")
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|
require (iStars == 0, s"${name} (a splitter) cannot appear left of a :*=; did you mean :=*?${lazyModule.line}")
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|
(0, iKnown)
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}
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protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] = {
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require (p.size == 0 || n % p.size == 0, s"Diplomacy bug; splitter inputs do not divide outputs")
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|
val out = dFn(SplitterArg(n, p))
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|
require (out.size == n, s"${name} created the wrong number of outputs from inputs${lazyModule.line}")
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|
out
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}
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protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] = {
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|
require (n == 0 || p.size % n == 0, s"Diplomacy bug; splitter outputs indivisable by inputs")
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|
val out = uFn(SplitterArg(n, p))
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|
require (out.size == n, s"${name} created the wrong number of inputs from outputs${lazyModule.line}")
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|
out
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|
}
|
|
}
|
|
|
|
class SplitterNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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|
dFn: SplitterArg[D] => Seq[D],
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|
uFn: SplitterArg[U] => Seq[U],
|
|
numPO: Range.Inclusive = 1 to 999,
|
|
numPI: Range.Inclusive = 1 to 999)
|
|
extends MixedSplitterNode[D, U, EI, B, D, U, EO, B](imp, imp)(dFn, uFn, numPO, numPI)
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|
|
|
class IdentityNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])
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|
extends AdapterNode(imp)({s => s}, {s => s})
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|
|
|
class OutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp)
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|
{
|
|
override val externalIn: Boolean = false
|
|
override val externalOut: Boolean = true
|
|
override lazy val bundleIn = bundleOut
|
|
}
|
|
|
|
class InputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B]) extends IdentityNode(imp)
|
|
{
|
|
override val externalIn: Boolean = true
|
|
override val externalOut: Boolean = false
|
|
|
|
override lazy val bundleOut = bundleIn
|
|
}
|
|
|
|
class SourceNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
|
extends MixedNode(imp, imp)(po.size to po.size, 0 to 0)
|
|
{
|
|
override val externalIn: Boolean = false
|
|
override val externalOut: Boolean = true
|
|
|
|
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
|
require (oStars <= 1, s"${name} (a source) appears right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
|
|
require (iStars == 0, s"${name} (a source) cannot appear left of a :*=${lazyModule.line}")
|
|
require (iKnown == 0, s"${name} (a source) cannot appear left of a :=${lazyModule.line}")
|
|
require (po.size >= oKnown, s"${name} (a source) has ${oKnown} outputs out of ${po.size}; cannot assign ${po.size - oKnown} edges to resolve :=*${lazyModule.line}")
|
|
(0, po.size - oKnown)
|
|
}
|
|
protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = po
|
|
protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = Seq()
|
|
|
|
override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut }
|
|
}
|
|
|
|
class SinkNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
|
extends MixedNode(imp, imp)(0 to 0, pi.size to pi.size)
|
|
{
|
|
override val externalIn: Boolean = true
|
|
override val externalOut: Boolean = false
|
|
|
|
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
|
|
require (iStars <= 1, s"${name} (a sink) appears left of a :*= ${iStars} times; at most once is allowed${lazyModule.line}")
|
|
require (oStars == 0, s"${name} (a sink) cannot appear right of a :=*${lazyModule.line}")
|
|
require (oKnown == 0, s"${name} (a sink) cannot appear right of a :=${lazyModule.line}")
|
|
require (pi.size >= iKnown, s"${name} (a sink) has ${iKnown} inputs out of ${pi.size}; cannot assign ${pi.size - iKnown} edges to resolve :*=${lazyModule.line}")
|
|
(pi.size - iKnown, 0)
|
|
}
|
|
protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq()
|
|
protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi
|
|
|
|
override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
|
|
}
|
|
|
|
class BlindOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
|
extends SinkNode(imp)(pi)
|
|
{
|
|
override val externalIn: Boolean = false
|
|
override val flip = true
|
|
override lazy val bundleOut = bundleIn
|
|
}
|
|
|
|
class BlindInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
|
extends SourceNode(imp)(po)
|
|
{
|
|
override val externalOut: Boolean = false
|
|
override val flip = true
|
|
override lazy val bundleIn = bundleOut
|
|
}
|
|
|
|
class InternalOutputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(pi: Seq[U])
|
|
extends SinkNode(imp)(pi)
|
|
{
|
|
override val externalIn: Boolean = false
|
|
override val externalOut: Boolean = false
|
|
override val wire = true
|
|
override lazy val bundleOut = bundleIn
|
|
}
|
|
|
|
class InternalInputNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(po: Seq[D])
|
|
extends SourceNode(imp)(po)
|
|
{
|
|
override val externalIn: Boolean = false
|
|
override val externalOut: Boolean = false
|
|
override val wire = true
|
|
override lazy val bundleIn = bundleOut
|
|
}
|