b8098d18be
The reason for the :=? operator was for when you have an adapter chain whose direction of cardinality you could not know. We used explicit directives to tell these compositions which way to go. Unfortunately, that makes the API leaky. You think the chain of adapters is just one adapter, but you have to use strange Cardinality scopes to use it. That's just bad. The new :*=* just automagically figures it out from the graph.
56 lines
1.8 KiB
Scala
56 lines
1.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class FrontBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.default
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) extends TLBusParams
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case object FrontBusKey extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
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private val master_buffer = LazyModule(new TLBuffer(params.masterBuffering))
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private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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master_buffer.suggestName(s"${busName}_master_TLBuffer")
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master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
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master_fixer.node :=* master_buffer.node
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inwardNode :=* master_fixer.node
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def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=* _)
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}
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def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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TLBuffer.chain(addBuffers).foldLeft(master_buffer.node:TLInwardNode)(_ :=* _)
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}
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def fromCoherentChip: TLInwardNode = inwardNode
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def toSystemBus : TLOutwardNode = TLBuffer(params.slaveBuffering) :=* xbar.node
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasFrontBus extends HasSystemBus {
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private val frontbusParams = p(FrontBusKey)
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val frontbusBeatBytes = frontbusParams.beatBytes
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val fbus = LazyModule(new FrontBus(frontbusParams))
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FlipRendering { implicit p => sbus.fromFrontBus :=* fbus.toSystemBus }
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}
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