151 lines
4.8 KiB
Python
Executable File
151 lines
4.8 KiB
Python
Executable File
#! /usr/bin/env python
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# See LICENSE for license details.
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import sys
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import math
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use_latches = 0
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def parse_line(line):
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name = ''
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width = 0
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depth = 0
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ports = ''
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mask_gran = 1
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tokens = line.split()
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i = 0
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for i in xrange(0,len(tokens),2):
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s = tokens[i]
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if s == 'name':
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name = tokens[i+1]
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elif s == 'width':
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width = int(tokens[i+1])
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elif s == 'depth':
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depth = int(tokens[i+1])
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elif s == 'ports':
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ports = tokens[i+1].split(',')
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elif s == 'mask_gran':
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# currently used only for fpga, but here for .conf format compatability
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mask_gran = int(tokens[i+1])
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else:
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sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
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return (name, width, depth, ports)
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def gen_mem(name, width, depth, ports):
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addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
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port_spec = ['input CLK', 'input RST', 'input init']
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readports = []
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writeports = []
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latchports = []
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rwports = []
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decl = []
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combinational = []
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sequential = []
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maskedports = {}
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for pid in range(len(ports)):
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ptype = ports[pid]
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if ptype[0:1] == 'm':
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ptype = ptype[1:]
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maskedports[pid] = pid
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if ptype == 'read':
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port_spec.append('input [%d:0] R%dA' % (addr_width-1, pid))
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port_spec.append('input R%dE' % pid)
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port_spec.append('output [%d:0] R%dO' % (width-1, pid))
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readports.append(pid)
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elif ptype == 'write':
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port_spec.append('input [%d:0] W%dA' % (addr_width-1, pid))
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port_spec.append('input W%dE' % pid)
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port_spec.append('input [%d:0] W%dI' % (width-1, pid))
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if pid in maskedports:
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port_spec.append('input [%d:0] W%dM' % (width-1, pid))
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if not use_latches or pid in maskedports:
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writeports.append(pid)
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else:
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latchports.append(pid)
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elif ptype == 'rw':
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port_spec.append('input [%d:0] RW%dA' % (addr_width-1, pid))
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port_spec.append('input RW%dE' % pid)
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port_spec.append('input RW%dW' % pid)
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if pid in maskedports:
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port_spec.append('input [%d:0] RW%dM' % (width-1, pid))
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port_spec.append('input [%d:0] RW%dI' % (width-1, pid))
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port_spec.append('output [%d:0] RW%dO' % (width-1, pid))
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rwports.append(pid)
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else:
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sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
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nr = len(readports)
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nw = len(writeports)
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nrw = len(rwports)
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masked = len(maskedports)>0
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tup = (depth, width, nr, nw, nrw, masked)
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decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
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decl.append('`ifndef SYNTHESIS')
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decl.append(' integer initvar;')
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decl.append(' initial begin')
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decl.append(' #0.002;')
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decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
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decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
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decl.append(' end')
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decl.append('`endif')
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for pid in readports:
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decl.append('reg [%d:0] reg_R%dA;' % (addr_width-1, pid))
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sequential.append('if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid))
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combinational.append('assign R%dO = ram[reg_R%dA];' % (pid, pid))
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for pid in rwports:
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decl.append('reg [%d:0] reg_RW%dA;' % (addr_width-1, pid))
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sequential.append('if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid))
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combinational.append('assign RW%dO = ram[reg_RW%dA];' % (pid, pid))
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for pid in latchports:
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decl.append('reg [%d:0] latch_W%dA;' % (addr_width-1, pid))
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decl.append('reg [%d:0] latch_W%dI;' % (width-1, pid))
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decl.append('reg latch_W%dE;' % (pid))
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combinational.append('always @(*) begin')
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combinational.append(' if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid))
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combinational.append(' if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid))
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combinational.append(' if (!CLK) latch_W%dE <= W%dE;' % (pid, pid))
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combinational.append('end')
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combinational.append('always @(*)')
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combinational.append(' if (CLK && latch_W%dE)' % (pid))
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combinational.append(' ram[latch_W%dA] <= latch_W%dI;' % (pid, pid))
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decl.append("integer i;")
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sequential.append("for (i = 0; i < %d; i=i+1) begin" % width)
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for pid in writeports:
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mask = (' && W%dM[i]' % pid) if pid in maskedports else ''
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sequential.append(" if (W%dE%s) ram[W%dA][i] <= W%dI[i];" % (pid, mask, pid, pid))
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for pid in rwports:
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mask = (' && RW%dM[i]' % pid) if pid in maskedports else ''
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sequential.append(" if (RW%dE && RW%dW%s) ram[RW%dA][i] <= RW%dI[i];" % (pid, pid, mask, pid, pid))
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sequential.append("end")
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body = "\
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%s\n\
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always @(posedge CLK) begin\n\
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%s\n\
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end\n\
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%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
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s = "module %s(\n\
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%s\n\
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);\n\
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\n\
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%s\
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\n\
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endmodule\n" % (name, ',\n '.join(port_spec), body)
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return s
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def main():
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if len(sys.argv) < 2:
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sys.exit('Please give a .conf file as input')
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for line in open(sys.argv[1]):
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print gen_mem(*parse_line(line))
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if __name__ == '__main__':
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main()
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