117 lines
3.3 KiB
Scala
117 lines
3.3 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import rocket.Util._
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import junctions._
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class TestHarness(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val dut = Module(new Top(p))
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// This test harness isn't especially flexible yet
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require(dut.io.mem_clk.isEmpty)
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require(dut.io.mem_rst.isEmpty)
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require(dut.io.mem_ahb.isEmpty)
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require(dut.io.mem_tl.isEmpty)
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require(dut.io.bus_clk.isEmpty)
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require(dut.io.bus_rst.isEmpty)
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require(dut.io.bus_axi.isEmpty)
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require(dut.io.mmio_clk.isEmpty)
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require(dut.io.mmio_rst.isEmpty)
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require(dut.io.mmio_axi.isEmpty)
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require(dut.io.mmio_ahb.isEmpty)
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require(dut.io.mmio_tl.isEmpty)
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require(dut.io.debug_clk.isEmpty)
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require(dut.io.debug_rst.isEmpty)
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require(dut.io.debug_rst.isEmpty)
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require(dut.io.extra.elements.isEmpty)
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for (int <- dut.io.interrupts)
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int := false
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if (dut.io.mem_axi.nonEmpty) {
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val memSize = p(GlobalAddrMap)("mem").size
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require(memSize % dut.io.mem_axi.size == 0)
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for (axi <- dut.io.mem_axi)
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Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
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}
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val dtm = Module(new SimDTM)
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dut.io.debug <> dtm.io.debug
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dtm.io.clk := clock
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dtm.io.reset := reset
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io.success := dut.io.success.getOrElse(dtm.io.exit === 1)
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when (dtm.io.exit >= 2) {
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printf("*** FAILED *** (exit code = %d)\n", dtm.io.exit >> 1)
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stop(1)
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}
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}
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class SimAXIMem(size: BigInt)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val axi = new NastiIO().flip
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}
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val rValid = Reg(init = Bool(false))
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val ar = RegEnable(io.axi.ar.bits, io.axi.ar.fire())
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io.axi.ar.ready := !rValid
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when (io.axi.ar.fire()) { rValid := true }
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when (io.axi.r.fire()) {
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assert(ar.burst === NastiConstants.BURST_INCR)
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ar.addr := ar.addr + (UInt(1) << ar.size)
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ar.len := ar.len - 1
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when (ar.len === UInt(0)) { rValid := false }
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}
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val w = io.axi.w.bits
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require((size * 8) % w.data.getWidth == 0)
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val depth = (size * 8) / w.data.getWidth
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val mem = Mem(depth.toInt, w.data)
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val wValid = Reg(init = Bool(false))
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val bValid = Reg(init = Bool(false))
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val aw = RegEnable(io.axi.aw.bits, io.axi.aw.fire())
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io.axi.aw.ready := !wValid && !bValid
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io.axi.w.ready := wValid
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when (io.axi.b.fire()) { bValid := false }
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when (io.axi.aw.fire()) { wValid := true }
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when (io.axi.w.fire()) {
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assert(aw.burst === NastiConstants.BURST_INCR)
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aw.addr := aw.addr + (UInt(1) << aw.size)
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aw.len := aw.len - 1
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when (aw.len === UInt(0)) {
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wValid := false
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bValid := true
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}
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def row = mem((aw.addr >> log2Ceil(w.data.getWidth/8))(log2Ceil(depth)-1, 0))
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val mask = FillInterleaved(8, w.strb)
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val newData = mask & w.data | ~mask & row
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row := newData
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}
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io.axi.b.valid := bValid
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io.axi.b.bits.id := aw.id
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io.axi.b.bits.resp := UInt(0)
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io.axi.r.valid := rValid
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io.axi.r.bits.id := ar.id
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io.axi.r.bits.data := mem((ar.addr >> log2Ceil(w.data.getWidth/8))(log2Ceil(depth)-1, 0))
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io.axi.r.bits.resp := UInt(0)
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io.axi.r.bits.last := ar.len === UInt(0)
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}
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class SimDTM(implicit p: Parameters) extends BlackBox {
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val io = new Bundle {
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val clk = Clock(INPUT)
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val reset = Bool(INPUT)
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val debug = new uncore.devices.DebugBusIO
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val exit = UInt(OUTPUT, 32)
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}
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}
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