262 lines
10 KiB
Scala
262 lines
10 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import coreplex._
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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/** Options for memory bus interface */
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object BusType {
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sealed trait EnumVal
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case object AXI extends EnumVal
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case object AHB extends EnumVal
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case object TL extends EnumVal
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val busTypes = Seq(AXI, AHB, TL)
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}
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/** Memory channel controls */
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case object TMemoryChannels extends Field[BusType.EnumVal]
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/** External MMIO controls */
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case object NExtMMIOAXIChannels extends Field[Int]
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case object NExtMMIOAHBChannels extends Field[Int]
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case object NExtMMIOTLChannels extends Field[Int]
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/** External Bus controls */
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case object NExtBusAXIChannels extends Field[Int]
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/** Async configurations */
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case object AsyncBusChannels extends Field[Boolean]
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case object AsyncDebugBus extends Field[Boolean]
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case object AsyncMemChannels extends Field[Boolean]
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case object AsyncMMIOChannels extends Field[Boolean]
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/** External address map settings */
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case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
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case object ExtIOAddrMapEntries extends Field[Seq[AddrMapEntry]]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[Parameters => Coreplex]
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/** Function for connecting coreplex extra ports to top-level extra ports */
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case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
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/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters {
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implicit val p: Parameters
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lazy val tMemChannels = p(TMemoryChannels)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
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lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
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lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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lazy val exportBus = p(ExportBusPort)
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lazy val exportMMIO = p(ExportMMIOPort)
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}
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class MemBackupCtrlIO extends Bundle {
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val en = Bool(INPUT)
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val in_valid = Bool(INPUT)
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val out_ready = Bool(INPUT)
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val out_valid = Bool(OUTPUT)
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}
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/** Top-level io for the chip */
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem_clk = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Clock(INPUT))) else None
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val mem_rst = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Bool (INPUT))) else None
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val bus_clk = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Clock(INPUT))) else None
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val bus_rst = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Bool (INPUT))) else None
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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val mmio_clk = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Clock(INPUT))) else None
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val mmio_rst = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Bool (INPUT))) else None
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val debug_clk = if (p(AsyncDebugBus)) Some(Clock(INPUT)) else None
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val debug_rst = if (p(AsyncDebugBus)) Some(Bool(INPUT)) else None
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val debug = new DebugBusIO()(p).flip
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val extra = p(ExtraTopPorts)(p)
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}
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object TopUtils {
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// Connect two Nasti interfaces with queues in-between
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def connectNasti(outer: NastiIO, inner: NastiIO)(implicit p: Parameters) {
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val mifDataBeats = p(MIFDataBeats)
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outer.ar <> Queue(inner.ar, 1)
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outer.aw <> Queue(inner.aw, 1)
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outer.w <> Queue(inner.w)
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inner.r <> Queue(outer.r)
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inner.b <> Queue(outer.b, 1)
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}
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def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val conv = Module(new NastiIOTileLinkIOConverter())
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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def connectTilelinkAhb(ahb: HastiMasterIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val bridge = Module(new AHBBridge(true))
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bridge.io.tl <> tl
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bridge.io.ahb
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}
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def connectTilelink(
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outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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outer.acquire <> Queue(inner.acquire)
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inner.grant <> Queue(outer.grant)
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}
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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implicit val p = topParams
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val coreplex = p(BuildCoreplex)(p)
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val periphery = Module(new Periphery()(innerParams))
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val io = new TopIO {
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val success = if (coreplex.hasSuccessFlag) Some(Bool(OUTPUT)) else None
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}
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io.success zip coreplex.io.success map { case (x, y) => x := y }
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if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
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periphery.io.mem_in <> coreplex.io.mem
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if (exportBus) { coreplex.io.bus.get <> periphery.io.bus_out.get }
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coreplex.io.debug <>
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(if (p(AsyncDebugBus))
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AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug)
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else io.debug)
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def asyncAxiTo(clocks: Seq[Clock], resets: Seq[Bool], inner_axis: Seq[NastiIO]): Seq[NastiIO] =
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(clocks, resets, inner_axis).zipped.map {
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case (clk, rst, in_axi) => AsyncNastiTo(clk, rst, in_axi)
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}
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def asyncAxiFrom(clocks: Seq[Clock], resets: Seq[Bool], outer_axis: Seq[NastiIO]): Seq[NastiIO] =
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(clocks, resets, outer_axis).zipped.map {
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case (clk, rst, out_axi) => AsyncNastiFrom(clk, rst, out_axi)
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}
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io.mmio_axi <>
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(if (p(AsyncMMIOChannels))
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asyncAxiTo(io.mmio_clk.get, io.mmio_rst.get, periphery.io.mmio_axi)
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else periphery.io.mmio_axi)
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io.mmio_ahb <> periphery.io.mmio_ahb
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io.mmio_tl <> periphery.io.mmio_tl
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io.mem_axi <>
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(if (p(AsyncMemChannels))
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asyncAxiTo(io.mem_clk.get, io.mem_rst.get, periphery.io.mem_axi)
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else periphery.io.mem_axi)
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io.mem_ahb <> periphery.io.mem_ahb
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io.mem_tl <> periphery.io.mem_tl
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periphery.io.bus_axi <>
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(if (p(AsyncBusChannels))
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asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi)
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else io.bus_axi)
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io.extra <> periphery.io.extra
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p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
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}
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class Periphery(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip
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val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams)) else None
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val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val extra = p(ExtraTopPorts)(p)
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}
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io.bus_out.map { tl_out =>
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val conv = Module(new TileLinkIONastiIOConverter)
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val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
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arb.io.master <> io.bus_axi
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conv.io.nasti <> conv.io.tl
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tl_out <> conv.io.tl
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}
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def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
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val mmio_axi_start = 0
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val mmio_axi_end = mmio_axi_start + p(NExtMMIOAXIChannels)
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val mmio_ahb_start = mmio_axi_end
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val mmio_ahb_end = mmio_ahb_start + p(NExtMMIOAHBChannels)
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val mmio_tl_start = mmio_ahb_end
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val mmio_tl_end = mmio_tl_start + p(NExtMMIOTLChannels)
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require (mmio_tl_end == ports.size)
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for (i <- 0 until ports.size) {
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if (mmio_axi_start <= i && i < mmio_axi_end) {
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TopUtils.connectTilelinkNasti(io.mmio_axi(i-mmio_axi_start), ports(i))
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} else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
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val ahbBridge = Module(new AHBBridge(true))
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io.mmio_ahb(i-mmio_ahb_start) <> ahbBridge.io.ahb
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ahbBridge.io.tl <> ports(i)
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} else if (mmio_tl_start <= i && i < mmio_tl_end) {
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TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
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} else {
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require(false, "Unconnected external MMIO port")
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}
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}
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}
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def buildMMIONetwork(implicit p: Parameters) = {
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val extAddrMap = p(GlobalAddrMap).subMap("io:ext")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, extAddrMap))
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mmioNetwork.io.in.head <> io.mmio_in.get
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for (device <- p(ExtraDevices)) {
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device.builder(mmioNetwork.port(device.addrMapEntry.name), io.extra, p)
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}
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val ext = p(ExtMMIOPorts).map(
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port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
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connectExternalMMIO(ext)(outermostMMIOParams)
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}
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if (exportMMIO) {
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buildMMIONetwork(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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for ((nasti, tl) <- io.mem_axi zip io.mem_in) {
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TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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nasti.ar.bits.cache := UInt("b0011")
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nasti.aw.bits.cache := UInt("b0011")
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}
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// Abuse the fact that zip takes the shorter of the two lists
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for ((ahb, tl) <- io.mem_ahb zip io.mem_in) {
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val bridge = Module(new AHBBridge(false)) // no atomics
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ahb <> bridge.io.ahb
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bridge.io.tl <> tl
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}
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for ((mem_tl, tl) <- io.mem_tl zip io.mem_in) {
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TopUtils.connectTilelink(mem_tl, tl)
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}
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}
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