142 lines
4.2 KiB
Scala
142 lines
4.2 KiB
Scala
package groundtest
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import Chisel._
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import rocket._
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import uncore.tilelink._
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import junctions._
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import scala.util.Random
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import scala.collection.mutable.ListBuffer
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import cde.{Parameters, Field}
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case object BuildGroundTest extends Field[Parameters => GroundTest]
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case class GroundTestTileSettings(
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uncached: Int = 0, cached: Int = 0, ptw: Int = 0, maxXacts: Int = 1)
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case object GroundTestKey extends Field[Seq[GroundTestTileSettings]]
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case object GroundTestId extends Field[Int]
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trait HasGroundTestConstants {
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val timeoutCodeBits = 4
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val errorCodeBits = 4
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}
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trait HasGroundTestParameters extends HasAddrMapParameters {
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implicit val p: Parameters
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val tileId = p(GroundTestId)
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val tileSettings = p(GroundTestKey)(tileId)
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val nUncached = tileSettings.uncached
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val nCached = tileSettings.cached
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val nPTW = tileSettings.ptw
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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}
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class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestors = Vec(n, new TLBPTWIO).flip
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}
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val req_arb = Module(new RRArbiter(new PTWReq, n))
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req_arb.io.in <> io.requestors.map(_.req)
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req_arb.io.out.ready := Bool(true)
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def vpn_to_ppn(vpn: UInt): UInt = vpn(ppnBits - 1, 0)
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class QueueChannel extends ParameterizedBundle()(p) {
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val ppn = UInt(width = ppnBits)
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val chosen = UInt(width = log2Up(n))
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}
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val s1_ppn = vpn_to_ppn(req_arb.io.out.bits.addr)
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val s2_ppn = RegEnable(s1_ppn, req_arb.io.out.valid)
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val s2_chosen = RegEnable(req_arb.io.chosen, req_arb.io.out.valid)
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val s2_valid = Reg(next = req_arb.io.out.valid)
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val s2_resp = Wire(new PTWResp)
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s2_resp.pte.ppn := s2_ppn
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s2_resp.pte.reserved_for_software := UInt(0)
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s2_resp.pte.d := Bool(true)
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s2_resp.pte.a := Bool(false)
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s2_resp.pte.g := Bool(false)
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s2_resp.pte.u := Bool(true)
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s2_resp.pte.r := Bool(true)
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s2_resp.pte.w := Bool(true)
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s2_resp.pte.x := Bool(false)
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s2_resp.pte.v := Bool(true)
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io.requestors.zipWithIndex.foreach { case (requestor, i) =>
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requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
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requestor.resp.bits := s2_resp
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requestor.status.vm := UInt("b01000")
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requestor.status.prv := UInt(PRV.S)
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requestor.invalidate := Bool(false)
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}
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}
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class GroundTestStatus extends Bundle with HasGroundTestConstants {
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val finished = Bool(OUTPUT)
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val timeout = Valid(UInt(width = timeoutCodeBits))
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val error = Valid(UInt(width = errorCodeBits))
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}
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class GroundTestIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasGroundTestParameters {
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val cache = Vec(nCached, new HellaCacheIO)
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val mem = Vec(nUncached, new ClientUncachedTileLinkIO)
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val ptw = Vec(nPTW, new TLBPTWIO)
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val status = new GroundTestStatus
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}
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abstract class GroundTest(implicit val p: Parameters) extends Module
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with HasGroundTestParameters {
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val io = new GroundTestIO
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}
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class GroundTestTile(resetSignal: Bool)
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(implicit val p: Parameters)
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extends Tile(resetSignal = resetSignal)(p)
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with HasGroundTestParameters {
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override val io = new TileIO {
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val success = Bool(OUTPUT)
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}
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val test = p(BuildGroundTest)(dcacheParams)
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val ptwPorts = ListBuffer.empty ++= test.io.ptw
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val memPorts = ListBuffer.empty ++= test.io.mem
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if (nCached > 0) {
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val dcache_io =
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if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
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else Module(new HellaCache()(dcacheParams)).io
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val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
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dcacheArb.io.requestor.zip(test.io.cache).foreach {
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case (requestor, cache) =>
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val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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dcacheIF.io.requestor <> cache
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requestor <> dcacheIF.io.cache
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}
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dcache_io.cpu <> dcacheArb.io.mem
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io.cached.head <> dcache_io.mem
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// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
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dcache_io.cpu.invalidate_lr := Bool(false)
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ptwPorts += dcache_io.ptw
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}
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if (ptwPorts.size > 0) {
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val ptw = Module(new DummyPTW(ptwPorts.size))
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ptw.io.requestors <> ptwPorts
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}
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require(memPorts.size == io.uncached.size)
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if (memPorts.size > 0) {
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io.uncached <> memPorts
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}
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io.success := test.io.status.finished
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}
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