* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
49 lines
1.5 KiB
Scala
49 lines
1.5 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.rocket.{HellaCache, RocketCoreParams}
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import freechips.rocketchip.tile._
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import scala.collection.mutable.ListBuffer
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trait GroundTestTileParams extends TileParams {
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val memStart: BigInt
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val maxRequests: Int
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val numGens: Int
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def build(i: Int, p: Parameters): GroundTestTile
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val icache = None
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val btb = None
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val rocc = Nil
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val core = RocketCoreParams(nPMPs = 0) //TODO remove this
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val cached = if(dcache.isDefined) 1 else 0
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val dataScratchpadBytes = 0
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}
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case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
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abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
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val slave = None
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val dcacheOpt = params.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
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dcacheOpt.foreach { tileBus.node := _.node }
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override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
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}
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class GroundTestTileBundle[+L <: GroundTestTile](_outer: L) extends BaseTileBundle(_outer) {
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val status = new GroundTestStatus
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}
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class GroundTestTileModule[+L <: GroundTestTile, +B <: GroundTestTileBundle[L]](_outer: L, _io: () => B) extends BaseTileModule(_outer, _io) {
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outer.dcacheOpt foreach { dcache =>
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val ptw = Module(new DummyPTW(1))
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ptw.io.requestors.head <> dcache.module.io.ptw
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}
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}
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