332 lines
14 KiB
Scala
332 lines
14 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import diplomacy._
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import scala.math.max
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case class TLManagerParameters(
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address: Seq[AddressSet],
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[BaseNode] = Seq(),
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// Supports both Acquire+Release+Finish of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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supportsLogical: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHint: TransferSizes = TransferSizes.none,
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// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
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fifoId: Option[Int] = None,
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customDTS: Option[String]= None)
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{
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require (!address.isEmpty)
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address.foreach { a => require (a.finite) }
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
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require (supportsPutFull.contains(supportsPutPartial))
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// Largest support transfer of all types
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val maxTransfer = List(
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supportsAcquire.max,
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supportsArithmetic.max,
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supportsLogical.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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val maxAddress = address.map(_.max).max
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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// Generate the config string (in future device tree)
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lazy val dts = customDTS.getOrElse {
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val header = s"${name} {\n"
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val middle = address.map { a =>
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require (a.contiguous) // Config String is not so flexible
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" addr 0x%x;\n size 0x%x;\n".format(a.base, a.mask+1)
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}
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val footer = "}\n"
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header + middle.reduce(_ + _) + footer
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}
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// The device had better not support a transfer larger than it's alignment
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val minAlignment = address.map(_.alignment).min
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require (minAlignment >= maxTransfer)
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}
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case class TLManagerPortParameters(
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managers: Seq[TLManagerParameters],
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beatBytes: Int,
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endSinkId: Int = 1,
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minLatency: Int = 0)
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{
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require (!managers.isEmpty)
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require (isPow2(beatBytes))
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require (endSinkId > 0)
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require (minLatency >= 0)
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// Bounds on required sizes
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def maxAddress = managers.map(_.maxAddress).max
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def maxTransfer = managers.map(_.maxTransfer).max
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// Operation sizes supported by all outward Managers
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val allSupportAcquire = managers.map(_.supportsAcquire) .reduce(_ intersect _)
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val allSupportArithmetic = managers.map(_.supportsArithmetic).reduce(_ intersect _)
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val allSupportLogical = managers.map(_.supportsLogical) .reduce(_ intersect _)
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val allSupportGet = managers.map(_.supportsGet) .reduce(_ intersect _)
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val allSupportPutFull = managers.map(_.supportsPutFull) .reduce(_ intersect _)
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val allSupportPutPartial = managers.map(_.supportsPutPartial).reduce(_ intersect _)
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val allSupportHint = managers.map(_.supportsHint) .reduce(_ intersect _)
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// Operation supported by at least one outward Managers
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val anySupportAcquire = managers.map(!_.supportsAcquire.none) .reduce(_ || _)
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val anySupportArithmetic = managers.map(!_.supportsArithmetic.none).reduce(_ || _)
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val anySupportLogical = managers.map(!_.supportsLogical.none) .reduce(_ || _)
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val anySupportGet = managers.map(!_.supportsGet.none) .reduce(_ || _)
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val anySupportPutFull = managers.map(!_.supportsPutFull.none) .reduce(_ || _)
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val anySupportPutPartial = managers.map(!_.supportsPutPartial.none).reduce(_ || _)
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val anySupportHint = managers.map(!_.supportsHint.none) .reduce(_ || _)
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// Which bits suffice to distinguish between all managers
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lazy val routingMask = AddressDecoder(managers.map(_.address))
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// These return Option[TLManagerParameters] for your convenience
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def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
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// The safe version will check the entire address
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def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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// The fast version assumes the address is valid
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def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Note: returns the actual fifoId + 1 or 0 if None
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def findFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
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def hasFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => Bool(m.fifoId.isDefined)))
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// Does this Port manage this ID/address?
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def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
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private def safe_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
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val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
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if (allSame) containsSafe(address) && member(managers(0)).containsLg(lgSize) else {
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Mux1H(findSafe(address), managers.map(member(_).containsLg(lgSize)))
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}
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}
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private def fast_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
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val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
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if (allSame) member(managers(0)).containsLg(lgSize) else {
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Mux1H(findFast(address), managers.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific address
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val supportsAcquireSafe = safe_helper(_.supportsAcquire) _
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val supportsArithmeticSafe = safe_helper(_.supportsArithmetic) _
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val supportsLogicalSafe = safe_helper(_.supportsLogical) _
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val supportsGetSafe = safe_helper(_.supportsGet) _
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val supportsPutFullSafe = safe_helper(_.supportsPutFull) _
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val supportsPutPartialSafe = safe_helper(_.supportsPutPartial) _
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val supportsHintSafe = safe_helper(_.supportsHint) _
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val supportsAcquireFast = fast_helper(_.supportsAcquire) _
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val supportsArithmeticFast = fast_helper(_.supportsArithmetic) _
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val supportsLogicalFast = fast_helper(_.supportsLogical) _
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val supportsGetFast = fast_helper(_.supportsGet) _
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val supportsPutFullFast = fast_helper(_.supportsPutFull) _
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val supportsPutPartialFast = fast_helper(_.supportsPutPartial) _
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val supportsHintFast = fast_helper(_.supportsHint) _
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}
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case class TLClientParameters(
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[BaseNode] = Seq(),
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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supportsLogical: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHint: TransferSizes = TransferSizes.none)
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{
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require (supportsPutFull.contains(supportsPutPartial))
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// We only support these operations if we support Probe (ie: we're a cache)
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require (supportsProbe.contains(supportsArithmetic))
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require (supportsProbe.contains(supportsLogical))
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require (supportsProbe.contains(supportsGet))
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require (supportsProbe.contains(supportsPutFull))
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require (supportsProbe.contains(supportsPutPartial))
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require (supportsProbe.contains(supportsHint))
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val maxTransfer = List(
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supportsProbe.max,
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supportsArithmetic.max,
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supportsLogical.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class TLClientPortParameters(
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clients: Seq[TLClientParameters],
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unsafeAtomics: Boolean = false,
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minLatency: Int = 0) // Atomics are executed as get+put
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{
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require (!clients.isEmpty)
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require (minLatency >= 0)
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// Require disjoint ranges for Ids
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clients.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.sourceId.overlaps(y.sourceId))
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})
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// Bounds on required sizes
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def endSourceId = clients.map(_.sourceId.end).max
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def maxTransfer = clients.map(_.maxTransfer).max
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// Operation sizes supported by all inward Clients
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val allSupportProbe = clients.map(_.supportsProbe) .reduce(_ intersect _)
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val allSupportArithmetic = clients.map(_.supportsArithmetic).reduce(_ intersect _)
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val allSupportLogical = clients.map(_.supportsLogical) .reduce(_ intersect _)
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val allSupportGet = clients.map(_.supportsGet) .reduce(_ intersect _)
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val allSupportPutFull = clients.map(_.supportsPutFull) .reduce(_ intersect _)
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val allSupportPutPartial = clients.map(_.supportsPutPartial).reduce(_ intersect _)
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val allSupportHint = clients.map(_.supportsHint) .reduce(_ intersect _)
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// Operation is supported by at least one client
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val anySupportProbe = clients.map(!_.supportsProbe.none) .reduce(_ || _)
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val anySupportArithmetic = clients.map(!_.supportsArithmetic.none).reduce(_ || _)
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val anySupportLogical = clients.map(!_.supportsLogical.none) .reduce(_ || _)
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val anySupportGet = clients.map(!_.supportsGet.none) .reduce(_ || _)
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val anySupportPutFull = clients.map(!_.supportsPutFull.none) .reduce(_ || _)
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val anySupportPutPartial = clients.map(!_.supportsPutPartial.none).reduce(_ || _)
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val anySupportHint = clients.map(!_.supportsHint.none) .reduce(_ || _)
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// These return Option[TLClientParameters] for your convenience
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def find(id: Int) = clients.find(_.sourceId.contains(id))
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// Synthesizable lookup methods
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def find(id: UInt) = Vec(clients.map(_.sourceId.contains(id)))
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def contains(id: UInt) = find(id).reduce(_ || _)
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private def safety_helper(member: TLClientParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
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val allSame = clients.map(member(_) == member(clients(0))).reduce(_ && _)
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if (allSame) member(clients(0)).containsLg(lgSize) else {
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Mux1H(find(id), clients.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific id
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val supportsProbe = safety_helper(_.supportsProbe) _
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val supportsArithmetic = safety_helper(_.supportsArithmetic) _
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val supportsLogical = safety_helper(_.supportsLogical) _
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val supportsGet = safety_helper(_.supportsGet) _
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val supportsPutFull = safety_helper(_.supportsPutFull) _
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val supportsPutPartial = safety_helper(_.supportsPutPartial) _
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val supportsHint = safety_helper(_.supportsHint) _
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}
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case class TLBundleParameters(
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addressBits: Int,
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dataBits: Int,
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sourceBits: Int,
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sinkBits: Int,
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sizeBits: Int)
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{
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// Chisel has issues with 0-width wires
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require (addressBits >= 1)
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require (dataBits >= 8)
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require (sourceBits >= 1)
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require (sinkBits >= 1)
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require (sizeBits >= 1)
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require (isPow2(dataBits))
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val addrLoBits = log2Up(dataBits/8)
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def union(x: TLBundleParameters) =
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TLBundleParameters(
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max(addressBits, x.addressBits),
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max(dataBits, x.dataBits),
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max(sourceBits, x.sourceBits),
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max(sinkBits, x.sinkBits),
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max(sizeBits, x.sizeBits))
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}
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object TLBundleParameters
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{
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def apply(client: TLClientPortParameters, manager: TLManagerPortParameters) =
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new TLBundleParameters(
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addressBits = log2Up(manager.maxAddress + 1),
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dataBits = manager.beatBytes * 8,
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sourceBits = log2Up(client.endSourceId),
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sinkBits = log2Up(manager.endSinkId),
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sizeBits = log2Up(log2Ceil(max(client.maxTransfer, manager.maxTransfer))+1))
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}
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case class TLEdgeParameters(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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{
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val maxTransfer = max(client.maxTransfer, manager.maxTransfer)
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val maxLgSize = log2Ceil(maxTransfer)
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// Sanity check the link...
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require (maxTransfer >= manager.beatBytes)
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val bundle = TLBundleParameters(client, manager)
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}
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case class TLAsyncManagerPortParameters(depth: Int, base: TLManagerPortParameters) { require (isPow2(depth)) }
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case class TLAsyncClientPortParameters(base: TLClientPortParameters)
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case class TLAsyncBundleParameters(depth: Int, base: TLBundleParameters) { require (isPow2(depth)) }
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case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters)
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{
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val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
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}
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object ManagerUnification
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{
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def apply(managers: Seq[TLManagerParameters]) = {
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// To be unified, devices must agree on all of these terms
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case class TLManagerKey(
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regionType: RegionType.T,
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executable: Boolean,
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lastNode: BaseNode,
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supportsAcquire: TransferSizes,
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supportsArithmetic: TransferSizes,
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supportsLogical: TransferSizes,
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supportsGet: TransferSizes,
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supportsPutFull: TransferSizes,
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supportsPutPartial: TransferSizes,
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supportsHint: TransferSizes)
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def key(x: TLManagerParameters) = TLManagerKey(
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regionType = x.regionType,
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executable = x.executable,
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lastNode = x.nodePath.last,
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supportsAcquire = x.supportsAcquire,
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supportsArithmetic = x.supportsArithmetic,
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supportsLogical = x.supportsLogical,
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supportsGet = x.supportsGet,
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supportsPutFull = x.supportsPutFull,
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supportsPutPartial = x.supportsPutPartial,
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supportsHint = x.supportsHint)
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val map = scala.collection.mutable.HashMap[TLManagerKey, TLManagerParameters]()
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managers.foreach { m =>
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val k = key(m)
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map.get(k) match {
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case None => map.update(k, m)
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case Some(n) => {
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map.update(k, m.copy(
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address = m.address ++ n.address,
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fifoId = None)) // Merging means it's not FIFO anymore!
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}
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}
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}
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map.values.map(m => m.copy(address = AddressSet.unify(m.address))).toList
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}
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}
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