Jacob Chang fc5eb7cc64 Fixed AsyncFifo with reset messaging

2016-10-25 16:45:08 -07:00

..

Arbiters.scala

move junctions utils into top-level utils package

2016-09-13 20:47:04 -07:00

AsyncQueue.scala

Fixed AsyncFifo with reset messaging

2016-10-25 16:45:08 -07:00

BlackBoxRegs.scala

Simplify AsyncResetReg

2016-10-08 21:29:40 -07:00

ClockDivider.scala

replace verilog clock divider with one written in Chisel

2016-09-22 11:32:29 -07:00

ConfigUtils.scala

make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs

2016-09-15 13:04:01 -07:00

Counters.scala

Move a bunch more things into util package

2016-09-29 14:23:42 -07:00

Crossing.scala

crossings: use flip not flip()

2016-10-10 13:13:31 -07:00

GeneratorUtils.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

GenericParameterizedBundle.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

HellaQueue.scala

move junctions utils into top-level utils package

2016-09-13 20:47:04 -07:00

LatencyPipe.scala

[util] move LatencyPipe into util

2016-09-15 13:30:34 -07:00

Misc.scala

don't use Scala to Chisel implicit conversions outside of rocket

2016-09-29 14:35:42 -07:00

Package.scala

Fix PopCountAtLeast, un-breaking BTB

2016-10-07 21:20:40 -07:00

PositionalMultiQueue.scala

PositionalMultiQueue: work around vcs Lint report

2016-10-10 11:21:49 -07:00

ReorderQueue.scala

move junctions utils into top-level utils package

2016-09-13 20:47:04 -07:00

Timer.scala

correctly initialize the active flag

2016-10-03 17:56:30 -07:00