63679bb019
They fit in the same part of the address space as DRAM would be, and are coherent (because they are not cacheable). They are currently limited to single cores without DRAM. We intend to lift both restrictions, probably when we add support for heterogeneous tiles.
394 lines
14 KiB
Scala
394 lines
14 KiB
Scala
// See LICENSE for license details.
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package coreplex
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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object ConfigUtils {
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def max_int(values: Int*): Int = {
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values.reduce((a, b) => max(a, b))
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}
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}
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import ConfigUtils._
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class BaseCoreplexConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val innerDataBits = site(XLen)
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case PAddrBits => 32
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 7
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case CacheIdBits => findBy(CacheName)
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case SplitMetadata => findBy(CacheName)
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => site(TLKey("L1toL2")).dataBitsPerBeat
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case NTLBEntries => 8
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case CacheIdBits => 0
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case SplitMetadata => false
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case DCacheKey => DCacheConfig(nMSHRs = site(Knob("L1D_MSHRS")))
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case DataScratchpadSize => 0
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//L2 Memory System Params
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case AmoAluOperandBits => site(XLen)
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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case NCachedTileLinkPorts => 1
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case NUncachedTileLinkPorts => 1
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//Tile Constants
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case BuildTiles => {
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val env = if(site(UseVM)) List("p","v") else List("p")
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site(FPUKey) foreach { case cfg =>
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TestGeneration.addSuite(rv32udBenchmarks)
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TestGeneration.addSuites(env.map(rv64ufNoDiv))
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TestGeneration.addSuites(env.map(rv64udNoDiv))
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if (cfg.divSqrt) {
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TestGeneration.addSuites(env.map(rv64uf))
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TestGeneration.addSuites(env.map(rv64ud))
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}
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}
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if (site(UseAtomics)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64ua else rv32ua))
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if (site(UseCompressed)) TestGeneration.addSuites(env.map(if (site(XLen) == 64) rv64uc else rv32uc))
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val (rvi, rvu) =
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if (site(XLen) == 64) ((if (site(UseVM)) rv64i else rv64pi), rv64u)
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else ((if (site(UseVM)) rv32i else rv32pi), rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuite(benchmarks)
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List.tabulate(site(NTiles)){ i => (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({
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case TileId => i
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case TLId => "L1toL2"
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case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
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})))
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}
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}
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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//Rocket Core Constants
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case CoreInstBits => if (site(UseCompressed)) 16 else 32
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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case RetireWidth => 1
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case UseVM => true
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case UseUser => true
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case UseDebug => true
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case NBreakpoints => 1
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case NPerfCounters => 0
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case NPerfEvents => 0
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case FastLoadWord => true
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case FastLoadByte => false
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case XLen => 64
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case FPUKey => Some(FPUConfig())
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case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))
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case UseAtomics => true
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case UseCompressed => true
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x1000)
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case MtvecInit => BigInt(0x1010)
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case MtvecWritable => true
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//Uncore Paramters
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
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maxClientXacts = max_int(
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// L1 cache
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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}
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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maxClientsPerPort = site(NBanksPerMemoryChannel),
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dataBeats = site(MIFDataBeats))
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case TLKey("L2toMMIO") => {
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = site(GlobalAddrMap).subMap("io").numSlaves,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes) * 8)
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}
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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case BootROMFile => "./bootrom/bootrom.img"
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case NTiles => Knob("NTILES")
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case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
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case BankIdLSB => 0
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case EnableL2Logging => false
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case ExtraCoreplexPorts => (p: Parameters) => new Bundle
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case RegressionTestNames => LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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"rv64ud-v-fadd",
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"rv64uf-v-fadd",
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"rv64um-v-mul",
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"rv64mi-p-breakpoint",
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"rv64uc-v-rvc",
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"rv64ud-v-structural",
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"rv64si-p-wfi",
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"rv64um-v-divw",
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"rv64ua-v-lrsc",
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"rv64ui-v-fence_i",
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"rv64ud-v-fcvt_w",
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"rv64uf-v-fmin",
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"rv64ui-v-sb",
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"rv64ua-v-amomax_d",
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"rv64ud-v-move",
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"rv64ud-v-fclass",
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"rv64ua-v-amoand_d",
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"rv64ua-v-amoxor_d",
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"rv64si-p-sbreak",
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"rv64ud-v-fmadd",
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"rv64uf-v-ldst",
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"rv64um-v-mulh",
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"rv64si-p-dirty")
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS_PER_MEM_CHANNEL" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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case _ => throw new CDEMatchError
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}
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)
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class WithNCores(n: Int) extends Config(
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knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
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class WithNBanksPerMemChannel(n: Int) extends Config(
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knobValues = {
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case "NBANKS_PER_MEM_CHANNEL" => n
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case _ => throw new CDEMatchError
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})
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class WithDataScratchpad(n: Int) extends Config(
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(pname,site,here) => pname match {
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case DataScratchpadSize => n
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case NSets if site(CacheName) == "L1D" => n / site(CacheBlockBytes)
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case _ => throw new CDEMatchError
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})
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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(site(NBanksPerMemoryChannel)*site(NMemoryChannels))) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
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case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel))
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case SplitMetadata => Knob("L2_SPLIT_METADATA")
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheId => id
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case CacheName => "L2Bank"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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case L2Replacer => () => new SeqRandom(site(NWays))
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case _ => throw new CDEMatchError
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048; case "L2_SPLIT_METADATA" => false; case _ => throw new CDEMatchError }
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)
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class WithBufferlessBroadcastHub extends Config(
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(pname, site, here) => pname match {
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new BufferlessBroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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})
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/**
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* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
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*
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* There is a very restrictive set of conditions under which the stateless
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* bridge will function properly. There can only be a single tile. This tile
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* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
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* uncached channel capable of writes (i.e. a RoCC accelerator).
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*
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* This is because the stateless bridge CANNOT generate probes, so if your
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* system depends on coherence between channels in any way,
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config (
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topDefinitions = (pname, site, here) => pname match {
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case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
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Module(new ManagerToClientStatelessBridge()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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},
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knobValues = {
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithPLRU extends Config(
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(pname, site, here) => pname match {
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case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
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case _ => throw new CDEMatchError
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})
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class WithL2Capacity(size_kb: Int) extends Config(
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knobValues = {
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case "L2_CAPACITY_IN_KB" => size_kb
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case _ => throw new CDEMatchError
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})
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class WithNL2Ways(n: Int) extends Config(
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knobValues = {
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case "L2_WAYS" => n
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case _ => throw new CDEMatchError
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})
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseVM => false
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case UseUser => false
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case UseAtomics => false
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case FPUKey => None
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case RegressionTestNames => LinkedHashSet(
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"rv32mi-p-ma_addr",
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"rv32mi-p-csr",
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"rv32ui-p-sh",
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"rv32ui-p-lh",
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"rv32uc-p-rvc",
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"rv32mi-p-sbreak",
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"rv32ui-p-sll")
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case _ => throw new CDEMatchError
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}
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)
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class WithBlockingL1 extends Config (
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knobValues = {
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithSmallCores extends Config (
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topDefinitions = { (pname,site,here) => pname match {
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case MulDivKey => Some(MulDivConfig())
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case FPUKey => None
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case NTLBEntries => 4
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case _ => throw new CDEMatchError
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}},
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knobValues = {
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 1
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case "L1D_MSHRS" => 0
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case _ => throw new CDEMatchError
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}
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)
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class WithRoccExample extends Config(
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(pname, site, here) => pname match {
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case BuildRoCC => Seq(
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RoccParameters(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
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RoccParameters(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => Module(new TranslatorExample()(p)),
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nPTWPorts = 1),
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RoccParameters(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
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case RoccMaxTaggedMemXacts => 1
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case _ => throw new CDEMatchError
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})
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class WithSplitL2Metadata extends Config(
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knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
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