49 lines
1.7 KiB
Scala
49 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.apb
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import Chisel._
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import config._
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import diplomacy._
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class APBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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{
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val node = APBSlaveNode(Seq(APBSlavePortParameters(
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Seq(APBSlaveParameters(
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address = List(address),
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regionType = RegionType.UNCACHED,
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executable = executable,
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supportsRead = true,
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supportsWrite = true)),
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beatBytes = beatBytes)))
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// We require the address range to include an entire beat (for the write mask)
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require ((address.mask & (beatBytes-1)) == beatBytes-1)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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val in = io.in(0)
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def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
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if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
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val mask = bigBits(address.mask >> log2Ceil(beatBytes))
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val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
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// Use single-ported memory with byte-write enable
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val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
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def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
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val read = in.psel && !in.penable && !in.pwrite
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when (in.psel && !in.penable && in.pwrite) {
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mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools)
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}
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in.pready := Bool(true)
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in.pslverr := Bool(false)
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in.prdata := holdUnless(mem.read(paddr, read).asUInt, RegNext(read))
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}
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}
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