e489c4226e
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes. It also makes it possible to connect optional crossbars that disappear. val x = TLXbar() x := master slave := x val y = TLXbar() x :=* y // only connect y if it gets used This will create crossbar x, but crossbar y will disappear.
49 lines
1.7 KiB
Scala
49 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.apb
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import scala.math.{min,max}
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class APBFanout()(implicit p: Parameters) extends LazyModule {
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val node = APBNexusNode(
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masterFn = { case Seq(m) => m },
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slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) })
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lazy val module = new LazyModuleImp(this) {
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if (node.edges.in.size >= 1) {
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require (node.edges.in.size == 1, "APBFanout does not support multiple masters")
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require (node.edges.out.size > 0, "APBFanout requires at least one slave")
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val (in, _) = node.in(0)
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// Require consistent bus widths
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val (io_out, edgesOut) = node.out.unzip
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val port0 = edgesOut(0).slave
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edgesOut.foreach { edge =>
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val port = edge.slave
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require (port.beatBytes == port0.beatBytes,
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s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}")
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}
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val port_addrs = edgesOut.map(_.slave.slaves.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
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val sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _)))
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(sel zip io_out) foreach { case (sel, out) =>
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out := in
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out.psel := sel && in.psel
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out.penable := sel && in.penable
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}
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in.pready := !Mux1H(sel, io_out.map(!_.pready))
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in.pslverr := Mux1H(sel, io_out.map(_.pslverr))
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in.prdata := Mux1H(sel, io_out.map(_.prdata))
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}
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}
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}
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