57 lines
1.8 KiB
Scala
57 lines
1.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tile._
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import scala.math.max
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case object TileId extends Field[Int]
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class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
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with HasMasterAXI4MemPort
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with HasPeripheryTestRAMSlave {
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val tileParams = p(GroundTestTilesKey)
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val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
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c.build(i, p.alterPartial {
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case TileKey => c
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case SharedMemoryTLEdge => sbus.busView
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})
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)}
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tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode }
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val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
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pbusRAM.node := pbus.toVariableWidthSlaves
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override lazy val module = new GroundTestCoreplexModule(this)
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}
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class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexModule(_outer)
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with HasMasterAXI4MemPortModuleImp {
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val success = IO(Bool(OUTPUT))
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outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
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val status = DebugCombiner(outer.tiles.map(_.module.io.status))
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success := status.finished
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}
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/** Adds a SRAM to the system for testing purposes. */
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trait HasPeripheryTestRAMSlave extends HasPeripheryBus {
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, pbus.beatBytes))
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testram.node := pbus.toVariableWidthSlaves
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}
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/** Adds a fuzzing master to the system for testing purposes. */
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trait HasPeripheryTestFuzzMaster extends HasPeripheryBus {
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val fuzzer = LazyModule(new TLFuzzer(5000))
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pbus.bufferFromMasters := fuzzer.node
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}
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