riscv/rocket-chip
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dd4a50c4529b16669a498ac76dba9b049888bd41
rocket-chip/src/main/scala/rocketchip
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Megan Wachs dd4a50c452 Add JTAG DTM and test support in simulation 
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
..
Configs.scala
Add JTAG DTM and test support in simulation
2016-08-19 16:08:17 -07:00
Devices.scala
move rocketchip package sources into its own subdirectory
2016-08-19 13:45:23 -07:00
Generator.scala
move rocketchip package sources into its own subdirectory
2016-08-19 13:45:23 -07:00
RocketChip.scala
Add JTAG DTM and test support in simulation
2016-08-19 16:08:17 -07:00
TestConfigs.scala
move rocketchip package sources into its own subdirectory
2016-08-19 13:45:23 -07:00
TestHarness.scala
Add JTAG DTM and test support in simulation
2016-08-19 16:08:17 -07:00