326 lines
13 KiB
Scala
326 lines
13 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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case object NBanksPerMemoryChannel extends Field[Int]
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/** Least significant bit of address used for bank partitioning */
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Number of exteral MMIO ports */
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case object NExtMMIOChannels extends Field[Int]
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/** Whether to divide HTIF clock */
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case object UseHtifClockDiv extends Field[Boolean]
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/** Function for building some kind of coherence manager agent */
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
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case object ConfigString extends Field[Array[Byte]]
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/** Number of L1 clients besides the CPU cores */
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case object ExtraL1Clients extends Field[Int]
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/** Number of external interrupt sources */
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case object NExtInterrupts extends Field[Int]
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/** Interrupt controller configuration */
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case object PLICKey extends Field[PLICConfig]
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case object UseStreamLoopback extends Field[Boolean]
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case object StreamLoopbackSize extends Field[Int]
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case object StreamLoopbackWidth extends Field[Int]
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/** Utility trait for quick access to some relevant parameters */
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trait HasTopLevelParameters {
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implicit val p: Parameters
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lazy val nTiles = p(NTiles)
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lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
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lazy val nUncachedTilePorts =
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p(TLKey("L1toL2")).nCachelessClients - p(ExtraL1Clients)
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lazy val htifW = p(HtifKey).width
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lazy val csrAddrBits = 12
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val nBanks = nMemChannels*nBanksPerMemChannel
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lazy val lsb = p(BankIdLSB)
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lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
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lazy val mifAddrBits = p(MIFAddrBits)
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lazy val mifDataBeats = p(MIFDataBeats)
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lazy val xLen = p(XLen)
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lazy val nSCR = p(HtifKey).nSCR
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lazy val scrAddrBits = log2Up(nSCR)
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lazy val scrDataBits = 64
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lazy val scrDataBytes = scrDataBits / 8
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//require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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class MemBackupCtrlIO extends Bundle {
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val en = Bool(INPUT)
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val in_valid = Bool(INPUT)
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val out_ready = Bool(INPUT)
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val out_valid = Bool(OUTPUT)
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}
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/** Top-level io for the chip */
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters {
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val host = new HostIO(htifW)
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}
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = Vec(nMemChannels, new NastiIO)
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
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}
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object TopUtils {
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// Connect two Nasti interfaces with queues in-between
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def connectNasti(outer: NastiIO, inner: NastiIO)(implicit p: Parameters) {
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val mifDataBeats = p(MIFDataBeats)
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outer.ar <> Queue(inner.ar)
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outer.aw <> Queue(inner.aw)
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outer.w <> Queue(inner.w, mifDataBeats)
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inner.r <> Queue(outer.r, mifDataBeats)
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inner.b <> Queue(outer.b)
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}
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def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val conv = Module(new NastiIOTileLinkIOConverter())
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conv.io.tl <> tl
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TopUtils.connectNasti(nasti, conv.io.nasti)
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}
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def makeBootROM()(implicit p: Parameters) = {
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val rom = java.nio.ByteBuffer.allocate(32)
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rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val addrHashMap = p(GlobalAddrHashMap)
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val resetToMemDist = addrHashMap("mem").start - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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rom.putInt(0x00000297 + resetToMemDist.toInt) // auipc t0, &mem - &here
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rom.putInt(0x00028067) // jr t0
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rom.putInt(0) // reserved
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rom.putInt(configStringAddr) // pointer to config string
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rom.putInt(0) // default trap vector
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rom.putInt(0) // ...
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rom.putInt(0) // ...
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rom.putInt(0) // ...
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rom.array() ++ p(ConfigString).toSeq
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}
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}
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/** Top-level module for the chip */
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//TODO: Remove this wrapper once multichannel DRAM controller is provided
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class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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implicit val p = topParams
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val io = new TopIO
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// Build an Uncore and a set of Tiles
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val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
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val uncore = Module(new Uncore()(innerTLParams))
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val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
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// Connect each tile to the HTIF
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for ((prci, tile) <- uncore.io.prci zip tileList) {
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tile.io.prci <> prci
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
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io.host <> uncore.io.host
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uncore.io.interrupts <> io.interrupts
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io.mmio <> uncore.io.mmio
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io.mem <> uncore.io.mem
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}
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/** Wrapper around everything that isn't a Tile.
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*
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* Usually this is clocked and/or place-and-routed separately from the Tiles.
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* Contains the Host-Target InterFace module (HTIF).
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*/
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class Uncore(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val host = new HostIO(htifW)
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val mem = Vec(nMemChannels, new NastiIO)
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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}
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val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
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val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
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outmemsys.io.incoherent := htif.io.cpu.map(_.reset)
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outmemsys.io.htif_uncached <> htif.io.mem
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = p(GlobalAddrHashMap)
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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scrFile.io.smi <> htif.io.scr
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// scrFile.io.scr <> (... your SCR connections ...)
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buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
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// Wire the htif to the memory port(s) and host interface
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io.mem <> outmemsys.io.mem
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if(p(UseHtifClockDiv)) {
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, io.host, htifW)
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} else {
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io.host <> htif.io.host
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}
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// Tie off HTIF CSR ports
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htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
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def buildMMIONetwork(implicit p: Parameters) = {
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val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
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val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
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val mmioNarrower = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap, ioBase))
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mmioNarrower.io.in <> outmemsys.io.mmio
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mmioNetwork.io.in.head <> mmioNarrower.io.out
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val rtc = Module(new RTC(p(NTiles)))
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val rtcAddr = ioAddrHashMap("int:rtc")
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require(rtc.size <= rtcAddr.region.size)
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rtc.io.tl <> mmioNetwork.io.out(rtcAddr.port)
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val plic = Module(new PLIC(p(PLICKey)))
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val plicAddr = ioAddrHashMap("int:plic")
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plic.io.tl <> mmioNetwork.io.out(plicAddr.port)
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := io.interrupts(i)
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plic.io.devices(i) <> gateway.io.plic
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}
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for (i <- 0 until nTiles) {
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val prci = Module(new PRCI)
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val prciAddr = ioAddrHashMap(s"int:prci$i")
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prci.io.tl <> mmioNetwork.io.out(prciAddr.port)
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prci.io.id := UInt(i)
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prci.io.interrupts.mtip := rtc.io.irqs(i)
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prci.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
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if (p(UseVM))
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prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S'))
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prci.io.interrupts.debug := Bool(false)
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io.prci(i) := prci.io.tile
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io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
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}
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val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
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val bootROMAddr = ioAddrHashMap("int:bootrom")
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bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
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val debugModule = Module(new ROMSlave(Seq())) // TODO
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val debugModuleAddr = ioAddrHashMap("int:debug")
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debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
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val mmioEndpoint = p(NExtMMIOChannels) match {
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case 0 => Module(new NastiErrorSlave).io
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case 1 => io.mmio(0)
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// The memory map presently has only one external I/O region
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}
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TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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}
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}
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/** The whole outer memory hierarchy, including a NoC, some kind of coherence
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* manager agent, and a converter from TileLink to MemIO.
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*/
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class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLevelParameters {
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val io = new Bundle {
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(nTiles, Bool()).asInput
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val mem = Vec(nMemChannels, new NastiIO)
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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val addrHashMap = p(GlobalAddrHashMap)
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = {
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val isMemory = addrHashMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory,
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if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
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UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(2,2,2,2,2)
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
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case TLId => "L1toL2"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMMIO"
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})))
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io.mmio <> mmioManager.io.outer
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> io.tiles_cached
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ Seq(io.htif_uncached)
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = p.alterPartial({ case TLId => "L2toMC" })
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val outermostTLParams = p.alterPartial({case TLId => "Outermost"})
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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// TODO: the code to print this stuff should live somewhere else
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println("Generated Address Map")
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for ((name, base, region) <- addrHashMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + region.size - 1}%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outermostTLParams))
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for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
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val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
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unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
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narrow.io.in <> unwrap.io.out
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icPort <> narrow.io.out
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}
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for ((nasti, tl) <- io.mem zip mem_ic.io.out) {
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TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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nasti.ar.bits.cache := UInt("b0011")
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nasti.aw.bits.cache := UInt("b0011")
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}
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}
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