129 lines
3.4 KiB
C++
129 lines
3.4 KiB
C++
// See LICENSE for license details.
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#include "mm_dramsim2.h"
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#include "mm.h"
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#include <DRAMSim.h>
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#include <iostream>
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#include <fstream>
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#include <list>
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#include <queue>
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#include <cstring>
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#include <cstdlib>
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#include <cassert>
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//#define DEBUG_DRAMSIM2
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using namespace DRAMSim;
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void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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assert(req.count(address));
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auto tag = req[address];
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req.erase(address);
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for (int i = 0; i < line_size/word_size; i++)
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{
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auto base = data + address + i*word_size;
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auto dat = std::vector<char>(base, base + word_size);
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resp.push(std::make_pair(tag, dat));
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}
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "[Callback] read complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
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#endif
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}
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void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "[Callback] write complete: id=%d , addr=0x%lx , cycle=%lu\n", id, address, clock_cycle);
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#endif
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}
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void power_callback(double a, double b, double c, double d)
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{
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//fprintf(stderr, "power callback: %0.3f, %0.3f, %0.3f, %0.3f\n",a,b,c,d);
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}
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void mm_dramsim2_t::init(size_t sz, int wsz, int lsz)
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{
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assert(lsz == 64); // assumed by dramsim2
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mm_t::init(sz, wsz, lsz);
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dummy_data.resize(word_size);
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assert(size % (1024*1024) == 0);
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mem = getMemorySystemInstance("DDR3_micron_64M_8B_x4_sg15.ini", "system.ini", "dramsim2_ini", "results", size/(1024*1024));
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TransactionCompleteCB *read_cb = new Callback<mm_dramsim2_t, void, unsigned, uint64_t, uint64_t>(this, &mm_dramsim2_t::read_complete);
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TransactionCompleteCB *write_cb = new Callback<mm_dramsim2_t, void, unsigned, uint64_t, uint64_t>(this, &mm_dramsim2_t::write_complete);
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mem->RegisterCallbacks(read_cb, write_cb, power_callback);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr,"Dramsim2 init successful\n");
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#endif
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}
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void mm_dramsim2_t::tick
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(
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bool req_cmd_val,
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bool req_cmd_store,
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uint64_t req_cmd_addr,
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uint64_t req_cmd_tag,
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bool req_data_val,
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void* req_data_bits,
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bool resp_rdy
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)
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{
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bool req_cmd_fire = req_cmd_val && req_cmd_ready();
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bool req_data_fire = req_data_val && req_data_ready();
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bool resp_fire = resp_valid() && resp_rdy;
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assert(!(req_cmd_fire && req_data_fire));
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if (resp_fire)
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resp.pop();
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if (req_cmd_fire)
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{
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// since the I$ can speculatively ask for address that are out of bounds
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auto byte_addr = (req_cmd_addr * line_size) % size;
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if (req_cmd_store)
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{
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store_inflight = 1;
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store_addr = byte_addr;
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Starting store transaction (addr=%lx ; tag=%ld ; cyc=%ld)\n", store_addr, req_cmd_tag, cycle);
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#endif
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}
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else
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{
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assert(!req.count(byte_addr));
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req[byte_addr] = req_cmd_tag;
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mem->addTransaction(false, byte_addr);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Adding load transaction (addr=%lx; cyc=%ld)\n", byte_addr, cycle);
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#endif
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}
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}
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if (req_data_fire)
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{
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memcpy(data + store_addr + store_count*word_size, req_data_bits, word_size);
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store_count = (store_count + 1) % (line_size/word_size);
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if (store_count == 0)
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{ // last chunch of cache line arrived.
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store_inflight = 0;
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mem->addTransaction(true, store_addr);
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#ifdef DEBUG_DRAMSIM2
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fprintf(stderr, "Adding store transaction (addr=%lx; cyc=%ld)\n", store_addr, cycle);
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#endif
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}
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}
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mem->update();
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cycle++;
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}
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