97 lines
2.7 KiB
Scala
97 lines
2.7 KiB
Scala
package uncore
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package constants
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import Chisel._
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import scala.math.max
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abstract trait CoherenceConfigConstants {
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val ENABLE_SHARING: Boolean
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val ENABLE_CLEAN_EXCLUSIVE: Boolean
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}
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trait UncoreConstants {
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val NGLOBAL_ACQ_XACTS = 8
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val NGLOBAL_REL_XACTS = 1
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val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_ACQ_XACTS+NGLOBAL_REL_XACTS)
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val CACHE_DATA_SIZE_IN_BYTES = 1 << 6
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}
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trait CacheConstants extends UncoreConstants {
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val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
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}
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trait TileLinkTypeConstants {
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val ACQUIRE_TYPE_MAX_BITS = 2
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val GRANT_TYPE_MAX_BITS = 3
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val PROBE_TYPE_MAX_BITS = 2
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val RELEASE_TYPE_MAX_BITS = 3
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}
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trait TileLinkSizeConstants extends
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TileLinkTypeConstants
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{
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val CLIENT_XACT_ID_MAX_BITS = 10
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val ACQUIRE_WRITE_MASK_BITS = 6
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val ACQUIRE_SUBWORD_ADDR_BITS = 3
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val ACQUIRE_ATOMIC_OP_BITS = 4
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}
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object MemoryOpConstants extends MemoryOpConstants
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trait MemoryOpConstants {
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val MT_X = Bits("b???", 3);
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val MT_B = Bits("b000", 3);
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val MT_H = Bits("b001", 3);
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val MT_W = Bits("b010", 3);
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val MT_D = Bits("b011", 3);
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val MT_BU = Bits("b100", 3);
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val MT_HU = Bits("b101", 3);
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val MT_WU = Bits("b110", 3);
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val M_SZ = 5
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val M_X = Bits("b?????");
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val M_XRD = Bits("b00000"); // int load
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val M_XWR = Bits("b00001"); // int store
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val M_PFR = Bits("b00010"); // prefetch with intent to read
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val M_PFW = Bits("b00011"); // prefetch with intent to write
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val M_FENCE = Bits("b00101"); // memory fence
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val M_XLR = Bits("b00110");
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val M_XSC = Bits("b00111");
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val M_XA_ADD = Bits("b01000");
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val M_XA_SWAP = Bits("b01001");
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val M_XA_AND = Bits("b01010");
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val M_XA_OR = Bits("b01011");
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val M_XA_MIN = Bits("b01100");
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val M_XA_MAX = Bits("b01101");
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val M_XA_MINU = Bits("b01110");
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val M_XA_MAXU = Bits("b01111");
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val M_INV = Bits("b10000"); // write back and invalidate line
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val M_CLN = Bits("b10001"); // write back line
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def isAMO(cmd: Bits) = cmd(3)
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def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
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def isRead(cmd: Bits) = cmd === M_XRD || cmd === M_XLR || isAMO(cmd)
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def isWrite(cmd: Bits) = cmd === M_XWR || cmd === M_XSC || isAMO(cmd)
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def isWriteIntent(cmd: Bits) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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}
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trait MemoryInterfaceConstants extends
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UncoreConstants with
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TileLinkSizeConstants
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{
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val MEM_TAG_BITS = max(CLIENT_XACT_ID_MAX_BITS, MASTER_XACT_ID_MAX_BITS)
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val MEM_DATA_BITS = 128
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val REFILL_CYCLES = CACHE_DATA_SIZE_IN_BYTES*8/MEM_DATA_BITS
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}
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object AddressConstants extends AddressConstants
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trait AddressConstants {
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val PADDR_BITS = 32
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val VADDR_BITS = 43;
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val PGIDX_BITS = 13;
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val PPN_BITS = PADDR_BITS-PGIDX_BITS;
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val VPN_BITS = VADDR_BITS-PGIDX_BITS;
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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}
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