52 lines
1.8 KiB
Scala
52 lines
1.8 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import coreplex._
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import rocketchip._
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/** Example Top with Periphery */
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class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(buildCoreplex)
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with PeripheryBootROM
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with PeripheryDebug
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with PeripheryExtInterrupts
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with PeripheryMasterMem
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with PeripheryMasterAXI4MMIO
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with PeripherySlave
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with DirectConnection {
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override lazy val module = new ExampleTopModule(new ExampleTopBundle(this))
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}
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class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer)
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with PeripheryBootROMBundle
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with PeripheryDebugBundle
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with PeripheryExtInterruptsBundle
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with PeripheryMasterMemBundle
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with PeripheryMasterAXI4MMIOBundle
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with PeripherySlaveBundle
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class ExampleTopModule[+B <: ExampleTopBundle[ExampleTop[BaseCoreplex]]](io: B) extends BaseTopModule(io)
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with PeripheryBootROMModule
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with PeripheryDebugModule
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with PeripheryExtInterruptsModule
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with PeripheryMasterMemModule
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with PeripheryMasterAXI4MMIOModule
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with PeripherySlaveModule
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with HardwiredResetVector
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with DirectConnectionModule
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)
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with PeripheryTestRAM {
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override lazy val module = new ExampleTopWithTestRAMModule(new ExampleTopWithTestRAMBundle(this))
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}
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class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer)
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with PeripheryTestRAMBundle
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class ExampleTopWithTestRAMModule[+B <: ExampleTopWithTestRAMBundle[ExampleTopWithTestRAM[BaseCoreplex]]](io: B) extends ExampleTopModule(io)
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with PeripheryTestRAMModule
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