61 lines
1.9 KiB
Scala
61 lines
1.9 KiB
Scala
/// See LICENSE for license details.
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package junctions
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import Chisel._
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object bigIntPow2 {
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def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
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}
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class ParameterizedBundle(implicit p: Parameters) extends Bundle {
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override def cloneType = this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type]
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}
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class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module {
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val io = new QueueIO(data, entries)
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require(entries > 1)
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val do_flow = Wire(Bool())
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val do_enq = io.enq.fire() && !do_flow
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val do_deq = io.deq.fire() && !do_flow
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val maybe_full = Reg(init=Bool(false))
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val enq_ptr = Counter(do_enq, entries)._1
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val (deq_ptr, deq_done) = Counter(do_deq, entries)
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when (do_enq != do_deq) { maybe_full := do_enq }
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val ptr_match = enq_ptr === deq_ptr
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val empty = ptr_match && !maybe_full
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val full = ptr_match && maybe_full
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val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
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do_flow := empty && io.deq.ready
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val ram = SeqMem(data, entries)
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when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
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val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
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val raddr = Mux(io.deq.valid, Mux(deq_done, UInt(0), deq_ptr + UInt(1)), deq_ptr)
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val ram_out_valid = Reg(next = ren)
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io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
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io.enq.ready := !full
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io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren))
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}
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class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module {
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val io = new QueueIO(data, entries)
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val fq = Module(new HellaFlowQueue(entries)(data))
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fq.io.enq <> io.enq
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io.deq <> Queue(fq.io.deq, 1, pipe = true)
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}
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object HellaQueue {
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def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = {
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val q = Module((new HellaQueue(entries)) { enq.bits })
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q.io.enq.valid := enq.valid // not using <> so that override is allowed
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q.io.enq.bits := enq.bits
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enq.ready := q.io.enq.ready
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q.io.deq
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}
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}
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