90 lines
2.7 KiB
Scala
90 lines
2.7 KiB
Scala
package groundtest.unittests
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.converters._
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import uncore.constants._
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import cde.Parameters
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class SmiConverterTestDriver(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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val nChecks = 32
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val count = Reg(init = UInt(0, log2Up(nChecks)))
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val addr = Cat(count, UInt(0, 2))
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val data = Fill(4, count)
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val (s_idle :: s_wreq :: s_wresp :: s_rreq :: s_rresp ::
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s_finished :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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when (state === s_idle && io.start) { state := s_wreq }
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when (state === s_wreq && io.mem.acquire.ready) { state := s_wresp }
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when (state === s_wresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_rreq
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} .otherwise {
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state := s_wreq
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}
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}
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when (state === s_rreq && io.mem.acquire.ready) { state := s_rresp }
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when (state === s_rresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_finished
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} .otherwise {
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state := s_rreq
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}
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}
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val blockOffsetBits = p(CacheBlockOffsetBits)
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val byteAddrBits = log2Up(p(TLKey(p(TLId))).writeMaskBits)
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io.mem.acquire.valid := (state === s_wreq) || (state === s_rreq)
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io.mem.acquire.bits := Mux(state === s_wreq,
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Put(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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data = Mux(count(0), data << UInt(32), data),
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wmask = Some(FillInterleaved(4, UIntToOH(count(0))))),
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Get(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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addr_byte = addr(byteAddrBits - 1, 0),
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operand_size = MT_W,
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alloc = Bool(false)))
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io.mem.grant.ready := (state === s_wresp) || (state === s_rresp)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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Mux(count(0),
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io.mem.grant.bits.data(63, 32) === data,
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io.mem.grant.bits.data(31, 0) === data),
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"Test Driver got incorrect data")
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io.finished := (state === s_finished)
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}
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class SmiConverterTest(implicit p: Parameters) extends UnitTest {
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val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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val smimem = Module(new SmiMem(32, 64))
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val conv = Module(new SmiIOTileLinkIOConverter(32, 6)(outermostParams))
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val driver = Module(new SmiConverterTestDriver()(outermostParams))
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conv.io.tl <> driver.io.mem
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smimem.io <> conv.io.smi
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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