244 lines
13 KiB
Scala
244 lines
13 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import Instructions._
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class ioCtrlDpathVec extends Bundle
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{
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val valid = Bool(INPUT)
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val inst = Bits(32, INPUT)
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val appvl0 = Bool(INPUT)
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val pfq = Bool(INPUT)
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val wen = Bool(OUTPUT)
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val fn = Bits(2, OUTPUT)
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val sel_vcmd = Bits(3, OUTPUT)
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val sel_vimm = Bits(1, OUTPUT)
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val sel_vimm2 = Bits(1, OUTPUT)
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}
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class ioCtrlVecInterface extends Bundle
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{
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val vcmdq_valid = Bool(OUTPUT)
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val vcmdq_ready = Bool(INPUT)
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val vximm1q_valid = Bool(OUTPUT)
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val vximm1q_ready = Bool(INPUT)
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val vximm2q_valid = Bool(OUTPUT)
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val vximm2q_ready = Bool(INPUT)
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val vcntq_valid = Bool(OUTPUT)
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val vcntq_ready = Bool(INPUT)
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val vpfcmdq_valid = Bool(OUTPUT)
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val vpfcmdq_ready = Bool(INPUT)
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val vpfximm1q_valid = Bool(OUTPUT)
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val vpfximm1q_ready = Bool(INPUT)
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val vpfximm2q_valid = Bool(OUTPUT)
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val vpfximm2q_ready = Bool(INPUT)
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val vpfcntq_valid = Bool(OUTPUT)
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val vpfcntq_ready = Bool(INPUT)
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val vcmdq_user_ready = Bool(INPUT)
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val vximm1q_user_ready = Bool(INPUT)
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val vximm2q_user_ready = Bool(INPUT)
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val vfence_ready = Bool(INPUT)
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val irq = Bool(INPUT)
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val irq_cause = UFix(5, INPUT)
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val exception = Bool(OUTPUT)
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val exception_ack_valid = Bool(INPUT)
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val exception_ack_ready = Bool(OUTPUT)
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val evac = Bool(OUTPUT)
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val kill = Bool(OUTPUT)
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val hold = Bool(OUTPUT)
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}
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class ioCtrlVec extends Bundle
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{
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val dpath = new ioCtrlDpathVec()
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val iface = new ioCtrlVecInterface()
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val s = Bool(INPUT)
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val sr_ev = Bool(INPUT)
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val exception = Bool(INPUT)
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val eret = Bool(INPUT)
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val replay = Bool(OUTPUT)
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val stalld = Bool(OUTPUT)
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val vfence_ready = Bool(OUTPUT)
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val irq = Bool(OUTPUT)
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val irq_cause = UFix(5, OUTPUT)
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}
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class rocketCtrlVec extends Component
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{
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val io = new ioCtrlVec()
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val veccs =
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ListLookup(io.dpath.inst,
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// appvlmask
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// | vcmdq
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// | | vximm1q
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// | | | vximm2q
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// | | | | vcntq
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// | | | | | vpfcmdq
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// | | | | | | vpfximm1q
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// | | | | | | | vpfximm2q
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// | | | | | | | | vpfcntq
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// wen | | | | | | | | | pfq
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// val vcmd vimm vimm2 | fn | | | | | | | | | | fence_cv
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// | | | | | | | | | | | | | | | | | xcptwait
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// | | | | | | | | | | | | | | | | | |
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List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array(
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VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
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VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N),
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VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
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VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N,N),
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FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N),
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FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N,N),
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VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N,N),
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VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N,N),
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VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N,N),
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VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N,N),
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VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N,N),
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VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N,N),
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VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
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VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N,N),
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VXCPTWAIT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y,N),
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VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N,Y)
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))
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val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
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val wb_vec_cmdq_enq :: wb_vec_ximm1q_enq :: wb_vec_ximm2q_enq :: wb_vec_cntq_enq :: veccs1 = veccs0
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val wb_vec_pfcmdq_enq :: wb_vec_pfximm1q_enq :: wb_vec_pfximm2q_enq :: wb_vec_pfcntq_enq :: veccs2 = veccs1
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val wb_vec_pfaq :: wb_vec_fence_cv :: wb_vec_xcptevac :: wb_vec_xcptkill :: wb_vec_xcptwait :: wb_vec_xcpthold :: Nil = veccs2
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val valid_common = io.dpath.valid && io.sr_ev && wb_vec_val && !(wb_vec_appvlmask && io.dpath.appvl0)
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val wb_vec_pfcmdq_enq_mask_pfq = wb_vec_pfcmdq_enq && (!wb_vec_pfaq || io.dpath.pfq)
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val wb_vec_pfximm1q_enq_mask_pfq = wb_vec_pfximm1q_enq && (!wb_vec_pfaq || io.dpath.pfq)
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val wb_vec_pfximm2q_enq_mask_pfq = wb_vec_pfximm2q_enq && (!wb_vec_pfaq || io.dpath.pfq)
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val wb_vec_pfcntq_enq_mask_pfq = wb_vec_pfcntq_enq && (!wb_vec_pfaq || io.dpath.pfq)
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val mask_wb_vec_cmdq_ready = !wb_vec_cmdq_enq || io.s && io.iface.vcmdq_ready || !io.s && io.iface.vcmdq_user_ready
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val mask_wb_vec_ximm1q_ready = !wb_vec_ximm1q_enq || io.s && io.iface.vximm1q_ready || !io.s && io.iface.vximm1q_user_ready
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val mask_wb_vec_ximm2q_ready = !wb_vec_ximm2q_enq || io.s && io.iface.vximm2q_ready || !io.s && io.iface.vximm2q_user_ready
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val mask_wb_vec_cntq_ready = !wb_vec_cntq_enq || io.iface.vcntq_ready
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val mask_wb_vec_pfcmdq_ready = !wb_vec_pfcmdq_enq_mask_pfq || io.iface.vpfcmdq_ready
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val mask_wb_vec_pfximm1q_ready = !wb_vec_pfximm1q_enq_mask_pfq || io.iface.vpfximm1q_ready
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val mask_wb_vec_pfximm2q_ready = !wb_vec_pfximm2q_enq_mask_pfq || io.iface.vpfximm2q_ready
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val mask_wb_vec_pfcntq_ready = !wb_vec_pfcntq_enq_mask_pfq || io.iface.vpfcntq_ready
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io.dpath.wen := wb_vec_wen.toBool
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io.dpath.fn := wb_vec_fn
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io.dpath.sel_vcmd := wb_sel_vcmd
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io.dpath.sel_vimm := wb_sel_vimm
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io.dpath.sel_vimm2 := wb_sel_vimm2
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io.iface.vcmdq_valid :=
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valid_common &&
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wb_vec_cmdq_enq && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vximm1q_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && wb_vec_ximm1q_enq && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vximm2q_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && wb_vec_ximm2q_enq && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vcntq_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && wb_vec_cntq_enq &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vpfcmdq_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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wb_vec_pfcmdq_enq_mask_pfq && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vpfximm1q_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && wb_vec_pfximm1q_enq_mask_pfq && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready
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io.iface.vpfximm2q_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq_mask_pfq && mask_wb_vec_pfcntq_ready
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io.iface.vpfcntq_valid :=
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valid_common &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && wb_vec_pfcntq_enq_mask_pfq
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io.replay := valid_common && (
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wb_vec_cmdq_enq && !io.iface.vcmdq_ready ||
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wb_vec_ximm1q_enq && !io.iface.vximm1q_ready ||
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wb_vec_ximm2q_enq && !io.iface.vximm2q_ready ||
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wb_vec_cntq_enq && !io.iface.vcntq_ready ||
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wb_vec_pfcmdq_enq_mask_pfq && !io.iface.vpfcmdq_ready ||
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wb_vec_pfximm1q_enq_mask_pfq && !io.iface.vpfximm1q_ready ||
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wb_vec_pfximm2q_enq_mask_pfq && !io.iface.vpfximm2q_ready ||
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wb_vec_pfcntq_enq_mask_pfq && !io.iface.vpfcntq_ready ||
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wb_vec_fence_cv && !io.iface.vfence_ready
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)
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val reg_xcptwait = Reg(resetVal = Bool(false))
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val do_xcptwait = valid_common && wb_vec_xcptwait && !io.replay
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when (io.iface.exception_ack_valid) { reg_xcptwait := Bool(false) }
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when (do_xcptwait) { reg_xcptwait := Bool(true) }
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io.iface.exception := io.exception && io.sr_ev
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io.iface.exception_ack_ready := reg_xcptwait
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val reg_hold = Reg(resetVal = Bool(false))
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when (valid_common && wb_vec_xcpthold) { reg_hold := Bool(true) }
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when (io.eret) { reg_hold := Bool(false) }
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io.iface.evac := valid_common && wb_vec_xcptevac.toBool
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io.iface.kill := valid_common && wb_vec_xcptkill.toBool
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io.iface.hold := reg_hold
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|
|
|
io.stalld := reg_xcptwait
|
|
io.vfence_ready := !io.sr_ev || io.iface.vfence_ready
|
|
io.irq := io.iface.irq
|
|
io.irq_cause := io.iface.irq_cause
|
|
}
|