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Arbiters.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AsyncBundle.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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AsyncQueue.scala
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Add 1-deep synchronizer register for output of AsyncQueue
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2017-08-28 17:18:54 -07:00 |
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AsyncResetReg.scala
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async_regs: Make modules have predictable names
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2017-08-24 15:33:53 -07:00 |
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Broadcaster.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ClockDivider.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Counters.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CRC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Crossing.scala
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syncregs: Use synchronizer primivites for LevelSyncCrossing
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2017-08-24 17:42:31 -07:00 |
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ECC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Frequency.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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GeneratorUtils.scala
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tilelink: add mask rom
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2017-07-31 21:34:04 -07:00 |
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GenericParameterizedBundle.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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HellaQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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HeterogeneousBag.scala
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HeterogenousBag: empty bags were being combined! (#956)
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2017-08-14 15:48:42 -07:00 |
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LatencyPipe.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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LCG.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Misc.scala
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Combine Coreplex and System Module Hierarchies (#875)
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2017-07-23 08:31:04 -07:00 |
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MultiWidthFifo.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PlusArg.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PositionalMultiQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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RationalCrossing.scala
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util: tweak rational crossings to avoid mux in source
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2017-07-31 15:10:15 -07:00 |
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ReduceOthers.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ReorderQueue.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Repeater.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Replacement.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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ResetCatchAndSync.scala
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syncregs: Make Reset catcher use the synchronizer primitive
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2017-08-24 17:26:38 -07:00 |
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ROMGenerator.scala
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tilelink: add mask rom
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2017-07-31 21:34:04 -07:00 |
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ShiftQueue.scala
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Optimize ShiftQueue for late-arriving deq.ready
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2017-08-04 22:06:37 -07:00 |
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SynchronizingReg.scala
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syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI
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2017-08-24 17:47:04 -07:00 |
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Timer.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
