136 lines
5.2 KiB
Scala
136 lines
5.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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case object TLBusDelayProbability extends Field[Double]
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/** Specifies widths of various attachement points in the SoC */
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trait TLBusParams {
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val beatBytes: Int
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val blockBytes: Int
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val masterBuffering: BufferParams
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val slaveBuffering: BufferParams
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def beatBits: Int = beatBytes * 8
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def blockBits: Int = blockBytes * 8
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def blockBeats: Int = blockBytes / beatBytes
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def blockOffset: Int = log2Up(blockBytes)
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}
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abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p: Parameters) extends TLBusParams {
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val beatBytes = params.beatBytes
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val blockBytes = params.blockBytes
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val masterBuffering = params.masterBuffering
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val slaveBuffering = params.slaveBuffering
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require(blockBytes % beatBytes == 0)
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private val delayProb = p(TLBusDelayProbability)
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protected val xbar = LazyModule(new TLXbar)
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xbar.suggestName(busName)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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master_buffer.suggestName(s"${busName}_master_TLBuffer")
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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slave_buffer.suggestName(s"${busName}_slave_TLBuffer")
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private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
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slave_frag.suggestName(s"${busName}_slave_TLFragmenter")
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private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
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slave_ww.suggestName(s"${busName}_slave_TLWidthWidget")
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private val delayedNode = if (delayProb > 0.0) {
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val firstDelay = LazyModule(new TLDelayer(delayProb))
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val flowDelay = LazyModule(new TLBuffer(BufferParams.flow))
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val secondDelay = LazyModule(new TLDelayer(delayProb))
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firstDelay.node :*= xbar.node
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flowDelay.node :*= firstDelay.node
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secondDelay.node :*= flowDelay.node
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secondDelay.node
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} else {
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xbar.node
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}
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xbar.node :=* master_buffer.node
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slave_buffer.node :*= delayedNode
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slave_frag.node :*= slave_buffer.node
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slave_ww.node :*= slave_buffer.node
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protected def outwardNode: TLOutwardNode = delayedNode
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protected def outwardBufNode: TLOutwardNode = slave_buffer.node
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protected def outwardFragNode: TLOutwardNode = slave_frag.node
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protected def outwardWWNode: TLOutwardNode = slave_ww.node
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protected def inwardNode: TLInwardNode = xbar.node
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protected def inwardBufNode: TLInwardNode = master_buffer.node
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protected def bufferChain(depth: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
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if (depth > 0) {
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val chain = List.fill(depth)(LazyModule(new TLBuffer(params)))
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name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
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(chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
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(chain.head.node, chain.last.node)
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} else {
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val dummy = LazyModule(new TLBuffer(BufferParams.none))
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name.foreach { n => dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")}
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(dummy.node, dummy.node)
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}
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}
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def bufferFromMasters: TLInwardNode = inwardBufNode
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def bufferToSlaves: TLOutwardNode = outwardBufNode
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def toAsyncSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
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source.node :*= outwardNode
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source.node
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}
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def toRationalSlaves(name: Option[String] = None): TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
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source.node :*= outwardNode
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source.node
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}
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def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
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def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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name.foreach {n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
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source.node :*= outwardFragNode
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source.node
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}
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def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
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source.node :*= outwardFragNode
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source.node
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}
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def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
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def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
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source.node := outwardWWNode
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source.node
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}
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def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
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source.node :*= outwardWWNode
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source.node
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}
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def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
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}
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