108 lines
4.4 KiB
Scala
108 lines
4.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.util._
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/** BareCoreplex is the root class for creating a coreplex sub-system */
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {
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lazy val dts = DTS(bindingTree)
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lazy val dtb = DTB(dts)
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lazy val json = JSON(bindingTree)
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}
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abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyModuleImp(_outer) {
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val outer = _outer
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ElaborationArtefacts.add("graphml", outer.graphML)
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ElaborationArtefacts.add("dts", outer.dts)
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ElaborationArtefacts.add("json", outer.json)
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ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
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println(outer.dts)
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}
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/** Base Coreplex class with no peripheral devices or ports added */
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abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with HasInterruptBus
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with HasSystemBus
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with HasPeripheryBus
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with HasMemoryBus {
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override val module: BaseCoreplexModule[BaseCoreplex]
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// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
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lazy val topManagers = Some(ManagerUnification(sharedMemoryTLEdge.manager.managers))
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ResourceBinding {
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val managers = topManagers.get
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val max = managers.flatMap(_.address).map(_.max).max
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val width = ResourceInt((log2Ceil(max)+31) / 32)
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val model = p(DTSModel)
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val compat = p(DTSCompat)
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val devCompat = (model +: compat).map(s => ResourceString(s + "-dev"))
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val socCompat = (model +: compat).map(s => ResourceString(s + "-soc"))
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devCompat.foreach { Resource(ResourceAnchors.root, "compat").bind(_) }
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socCompat.foreach { Resource(ResourceAnchors.soc, "compat").bind(_) }
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Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
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Resource(ResourceAnchors.root, "width").bind(width)
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Resource(ResourceAnchors.soc, "width").bind(width)
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Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
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managers.foreach { case manager =>
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val value = manager.toResource
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manager.resources.foreach { case resource =>
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resource.bind(value)
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}
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}
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}
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}
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abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) {
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println("Generated Address Map")
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private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1
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private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s"
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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value match {
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case r: ResourceAddress => List((path(1), r))
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case b: ResourceMapping => List((path(1), ResourceAddress(b.address, b.permissions)))
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case ResourceMap(value, _) => value.toList.flatMap { case (key, seq) => seq.flatMap(r => collect(key :: path, r)) }
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case _ => Nil
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}
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}
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private val ranges = collect(Nil, outer.bindingTree).groupBy(_._2).toList.flatMap { case (key, seq) =>
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AddressRange.fromSets(key.address).map { r => (r, key.permissions, seq.map(_._1)) }
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}.sortBy(_._1)
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private val json = ranges.map { case (range, ResourcePermissions(r, w, x, c, a), names) =>
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println(fmt.format(
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range.base,
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range.base+range.size,
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if (a) 'A' else ' ',
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if (r) 'R' else ' ',
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if (w) 'W' else ' ',
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if (x) 'X' else ' ',
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if (c) 'C' else ' ',
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names.mkString(", ")))
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s"""{"base":[${range.base}],"size":[${range.size}],"r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],"names":[${names.map('"'+_+'"').mkString(",")}]}"""
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}
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println("")
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ElaborationArtefacts.add("memmap.json", s"""{"mapping":[${json.mkString(",")}]}""")
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// Confirm that all of memory was described by DTS
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private val dtsRanges = AddressRange.unify(ranges.map(_._1))
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private val allRanges = AddressRange.unify(outer.topManagers.get.flatMap { m => AddressRange.fromSets(m.address) })
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if (dtsRanges != allRanges) {
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println("Address map described by DTS differs from physical implementation:")
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AddressRange.subtract(allRanges, dtsRanges).foreach { case r =>
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println(s"\texists, but undescribed by DTS: ${r}")
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}
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AddressRange.subtract(dtsRanges, allRanges).foreach { case r =>
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println(s"\tdoes not exist, but described by DTS: ${r}")
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}
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println("")
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}
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}
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