43 lines
1.2 KiB
Scala
43 lines
1.2 KiB
Scala
package uncore
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import Chisel._
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import junctions.{SmiIO, MMIOBase}
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import cde.Parameters
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class SCRIO(implicit p: Parameters) extends HtifBundle()(p) {
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val rdata = Vec(nSCR, Bits(INPUT, scrDataBits))
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val wen = Bool(OUTPUT)
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val waddr = UInt(OUTPUT, log2Up(nSCR))
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val wdata = Bits(OUTPUT, scrDataBits)
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}
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class SCRFile(implicit p: Parameters) extends HtifModule()(p) {
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val io = new Bundle {
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val smi = new SmiIO(scrDataBits, scrAddrBits).flip
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val scr = new SCRIO
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}
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val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits)))
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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scr_rdata(0) := UInt(nCores)
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scr_rdata(1) := UInt(p(MMIOBase) >> 20)
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val read_addr = Reg(init = UInt(0, scrAddrBits))
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val resp_valid = Reg(init = Bool(false))
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io.smi.req.ready := !resp_valid
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io.smi.resp.valid := resp_valid
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io.smi.resp.bits := scr_rdata(read_addr)
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io.scr.wen := io.smi.req.fire() && io.smi.req.bits.rw
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io.scr.wdata := io.smi.req.bits.data
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io.scr.waddr := io.smi.req.bits.addr
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when (io.smi.req.fire()) {
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read_addr := io.smi.req.bits.addr
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resp_valid := Bool(true)
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}
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when (io.smi.resp.fire()) { resp_valid := Bool(false) }
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}
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