226 lines
8.5 KiB
Scala
226 lines
8.5 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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import Chisel.ImplicitConversions._
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import junctions._
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import cde.{Parameters, Field}
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case object HtifKey extends Field[HtifParameters]
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case class HtifParameters(width: Int, nCores: Int, offsetBits: Int, nSCR: Int = 64)
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trait HasHtifParameters {
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implicit val p: Parameters
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val external = p(HtifKey)
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val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
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val dataBeats = p(TLKey(p(TLId))).dataBeats
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val w = external.width
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val nSCR = external.nSCR
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val scrAddrBits = log2Up(nSCR)
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val scrDataBits = 64
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val scrDataBytes = scrDataBits / 8
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val offsetBits = external.offsetBits
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val nCores = external.nCores
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}
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abstract class HtifModule(implicit val p: Parameters) extends Module with HasHtifParameters
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abstract class HtifBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasHtifParameters
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class HostIO(w: Int) extends Bundle {
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val clk = Bool(OUTPUT)
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val clk_edge = Bool(OUTPUT)
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val in = Decoupled(Bits(width = w)).flip
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val out = Decoupled(Bits(width = w))
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val debug_stats_csr = Bool(OUTPUT)
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}
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class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(nCores))
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val csr = new SmiIO(scrDataBits, 12).flip
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val debug_stats_csr = Bool(OUTPUT)
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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}
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class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
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val io = new Bundle {
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val host = new HostIO(w)
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val cpu = Vec(nCores, new HtifIO).flip
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val mem = new ClientUncachedTileLinkIO
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val scr = new SmiIO(scrDataBits, scrAddrBits)
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}
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io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_)
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// system is 'interesting' if any tile is 'interesting'
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val short_request_bits = 64
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val long_request_bits = short_request_bits + dataBits*dataBeats
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require(short_request_bits % w == 0)
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val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits
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val rx_count = Reg(init=UInt(0,rx_count_w))
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val rx_shifter = Reg(Bits(width = short_request_bits))
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val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w))
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val next_cmd = rx_shifter_in(3,0)
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val cmd = Reg(Bits())
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val size = Reg(Bits())
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val pos = Reg(Bits())
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val seqno = Reg(Bits())
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val addr = Reg(Bits())
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when (io.host.in.valid && io.host.in.ready) {
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rx_shifter := rx_shifter_in
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rx_count := rx_count + UInt(1)
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when (rx_count === UInt(short_request_bits/w-1)) {
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cmd := next_cmd
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size := rx_shifter_in(15,4)
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pos := rx_shifter_in(15,4+offsetBits-3)
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seqno := rx_shifter_in(23,16)
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addr := rx_shifter_in(63,24)
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}
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}
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val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
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val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
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val packet_ram_depth = long_request_bits/short_request_bits-1
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val packet_ram = Mem(packet_ram_depth, Bits(width = short_request_bits))
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when (rx_word_done && io.host.in.ready) {
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packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
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}
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6)
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val csr_addr = addr(io.cpu(0).csr.req.bits.addr.getWidth-1, 0)
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val csr_coreid = addr(log2Up(nCores)-1+20+1,20)
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val csr_wdata = packet_ram(0)
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val bad_mem_packet = size(offsetBits-1-3,0).orR || addr(offsetBits-1-3,0).orR
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val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, bad_mem_packet,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, size =/= UInt(1),
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Bool(true)))
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val tx_count = Reg(init=UInt(0, rx_count_w))
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val tx_subword_count = tx_count(log2Up(short_request_bits/w)-1,0)
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val tx_word_count = tx_count(rx_count_w-1, log2Up(short_request_bits/w))
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val packet_ram_raddr = tx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)
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when (io.host.out.valid && io.host.out.ready) {
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tx_count := tx_count + UInt(1)
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}
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val rx_done = rx_word_done && Mux(rx_word_count === UInt(0), next_cmd =/= cmd_writemem && next_cmd =/= cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UInt(0))
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val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr || cmd === cmd_writecr), size, UInt(0))
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val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UInt(0) && packet_ram_raddr.andR)
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val state_rx :: state_csr_req :: state_csr_resp :: state_mem_rreq :: state_mem_wreq :: state_mem_rresp :: state_mem_wresp :: state_tx :: Nil = Enum(UInt(), 8)
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val state = Reg(init=state_rx)
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val (cnt, cnt_done) = Counter((state === state_mem_wreq && io.mem.acquire.ready) ||
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(state === state_mem_rresp && io.mem.grant.valid), dataBeats)
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val rx_cmd = Mux(rx_word_count === UInt(0), next_cmd, cmd)
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when (state === state_rx && rx_done) {
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state := Mux(rx_cmd === cmd_readmem, state_mem_rreq,
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Mux(rx_cmd === cmd_writemem, state_mem_wreq,
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Mux(rx_cmd === cmd_readcr || rx_cmd === cmd_writecr, state_csr_req,
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state_tx)))
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}
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when (state === state_mem_wreq) {
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when (cnt_done) { state := state_mem_wresp }
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}
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when (state === state_mem_rreq) {
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when(io.mem.acquire.ready) { state := state_mem_rresp }
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}
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when (state === state_mem_wresp && io.mem.grant.valid) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << offsetBits-3)
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}
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when (state === state_mem_rresp && cnt_done) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << offsetBits-3)
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}
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when (state === state_tx && tx_done) {
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when (tx_word_count === tx_size) {
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rx_count := UInt(0)
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tx_count := UInt(0)
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}
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state := Mux(cmd === cmd_readmem && pos =/= UInt(0), state_mem_rreq, state_rx)
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}
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val n = dataBits/short_request_bits
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val mem_req_data = (0 until n).map { i =>
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val ui = UInt(i, log2Up(n))
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when (state === state_mem_rresp && io.mem.grant.valid) {
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packet_ram(Cat(io.mem.grant.bits.addr_beat, ui)) :=
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io.mem.grant.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
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}
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packet_ram(Cat(cnt, ui))
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}.reverse.reduce(_##_)
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val init_addr = addr.toUInt >> (offsetBits-3)
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io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq
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io.mem.acquire.bits := Mux(cmd === cmd_writemem,
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PutBlock(
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addr_block = init_addr,
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addr_beat = cnt,
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client_xact_id = UInt(0),
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data = mem_req_data),
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GetBlock(addr_block = init_addr))
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io.mem.grant.ready := Bool(true)
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val csrReadData = Reg(Bits(width = io.cpu(0).csr.resp.bits.getWidth))
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for (i <- 0 until nCores) {
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val my_reset = Reg(init=Bool(true))
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val cpu = io.cpu(i)
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val me = csr_coreid === UInt(i)
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cpu.csr.req.valid := state === state_csr_req && me && csr_addr =/= UInt(csr_RESET)
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cpu.csr.req.bits.rw := cmd === cmd_writecr
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cpu.csr.req.bits.addr := csr_addr
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cpu.csr.req.bits.data := csr_wdata
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cpu.reset := my_reset
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when (cpu.csr.req.fire()) { state := state_csr_resp }
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when (state === state_csr_req && me && csr_addr === UInt(csr_RESET)) {
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when (cmd === cmd_writecr) {
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my_reset := csr_wdata(0)
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}
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csrReadData := my_reset.toBits
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state := state_tx
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}
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cpu.csr.resp.ready := Bool(true)
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when (state === state_csr_resp && cpu.csr.resp.valid) {
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csrReadData := cpu.csr.resp.bits
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state := state_tx
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}
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}
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io.scr.req.valid := (state === state_csr_req && csr_coreid.andR)
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io.scr.req.bits.addr := addr(scrAddrBits - 1, 0).toUInt
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io.scr.req.bits.data := csr_wdata
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io.scr.req.bits.rw := (cmd === cmd_writecr)
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io.scr.resp.ready := Bool(true)
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when (io.scr.req.fire()) { state := state_csr_resp }
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when (state === state_csr_resp && io.scr.resp.valid) {
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csrReadData := io.scr.resp.bits
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state := state_tx
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
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val tx_data = Mux(tx_word_count === UInt(0), tx_header,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, csrReadData,
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packet_ram(packet_ram_raddr)))
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io.host.in.ready := state === state_rx
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io.host.out.valid := state === state_tx
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io.host.out.bits := tx_data >> Cat(tx_count(log2Up(short_request_bits/w)-1,0), Bits(0, log2Up(w)))
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}
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