78 lines
2.3 KiB
Scala
78 lines
2.3 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore._
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import rocket._
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import zscale._
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case object UseZscale extends Field[Boolean]
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case object BuildZscale extends Field[(Bool, Parameters) => Zscale]
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case object BootROMCapacity extends Field[Int]
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case object DRAMCapacity extends Field[Int]
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class ZscaleSystem(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val host = new HtifIO
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val jtag = new HastiMasterIO().flip
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val bootmem = new HastiSlaveIO().flip
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val dram = new HastiSlaveIO().flip
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val spi = new HastiSlaveIO().flip
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val led = new PociIO
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val corereset = new PociIO
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}
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val core = p(BuildZscale)(io.host.reset, p)
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val bootmem_afn = (addr: UInt) => addr(31, 14) === UInt(0)
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val sbus_afn = (addr: UInt) => addr(31, 29).orR
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val dram_afn = (addr: UInt) => addr(31, 26) === UInt(8)
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val spi_afn = (addr: UInt) => addr(31, 26) === UInt(9) && addr(25, 14) === UInt(0)
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val pbus_afn = (addr: UInt) => addr(31) === UInt(1)
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val led_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(0)
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val corereset_afn = (addr: UInt) => addr(31) === UInt(1) && addr(30, 10) === UInt(1)
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val xbar = Module(new HastiXbar(3, Seq(bootmem_afn, sbus_afn)))
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val sadapter = Module(new HastiSlaveToMaster)
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val sbus = Module(new HastiBus(Seq(dram_afn, spi_afn, pbus_afn)))
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val padapter = Module(new HastiToPociBridge)
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val pbus = Module(new PociBus(Seq(led_afn, corereset_afn)))
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core.io.host <> io.host
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xbar.io.masters(0) <> io.jtag
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xbar.io.masters(1) <> core.io.dmem
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xbar.io.masters(2) <> core.io.imem
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io.bootmem <> xbar.io.slaves(0)
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sadapter.io.in <> xbar.io.slaves(1)
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sbus.io.master <> sadapter.io.out
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io.dram <> sbus.io.slaves(0)
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io.spi <> sbus.io.slaves(1)
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padapter.io.in <> sbus.io.slaves(2)
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pbus.io.master <> padapter.io.out
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io.led <> pbus.io.slaves(0)
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io.corereset <> pbus.io.slaves(1)
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}
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class ZscaleTop(topParams: Parameters) extends Module {
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implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
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val io = new Bundle {
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val host = new HtifIO
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}
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val sys = Module(new ZscaleSystem)
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val bootmem = Module(new HastiSRAM(p(BootROMCapacity)/4))
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val dram = Module(new HastiSRAM(p(DRAMCapacity)/4))
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sys.io.host <> io.host
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bootmem.io <> sys.io.bootmem
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dram.io <> sys.io.dram
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}
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