96 lines
2.9 KiB
Scala
96 lines
2.9 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._;
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class ioDebug extends Bundle()
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{
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val error_mode = Bool('output);
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val log_control = Bool('output);
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}
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class ioHost(view: List[String] = null) extends Bundle(view)
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{
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val start = Bool('input);
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val from_wen = Bool('input);
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val from = Bits(32, 'input);
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val to = Bits(32, 'output);
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}
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class ioConsole(view: List[String] = null) extends Bundle(view)
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{
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val rdy = Bool('input);
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val valid = Bool('output);
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val bits = Bits(8, 'output);
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}
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class ioRocket extends Bundle()
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{
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val debug = new ioDebug();
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val console = new ioConsole();
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val host = new ioHost();
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val imem = new ioImem().flip();
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val dmem = new ioDmem().flip();
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}
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class rocketProc extends Component
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{
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val io = new ioRocket();
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val ctrl = new rocketCtrl();
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val dpath = new rocketDpath();
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val mem = new rocketMemory();
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val wb = new rocketWriteback();
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dpath.io.host ^^ io.host;
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dpath.io.debug ^^ io.debug;
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// dpath.io.wb <> wb.io;
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dpath.io.wb.wen <> wb.io.wb_wen;
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dpath.io.wb.waddr <> wb.io.wb_waddr;
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dpath.io.wb.wdata <> wb.io.wb_wdata;
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dpath.io.imem.req_addr ^^ io.imem.req_addr;
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dpath.io.imem.resp_data ^^ io.imem.resp_data;
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ctrl.io.ctrl <> dpath.io.ctrl;
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ctrl.io.dpath <> dpath.io.dpath;
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// ctrl.io.mem <> mem.io;
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ctrl.io.mem.mrq_val <> mem.io.mem_mrq_val;
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ctrl.io.mem.mrq_cmd <> mem.io.mem_mrq_cmd;
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ctrl.io.mem.mrq_type <> mem.io.mem_mrq_type;
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ctrl.io.mem.mrq_deq <> mem.io.mem_mrq_deq;
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ctrl.io.mem.xsdq_rdy <> mem.io.mem_xsdq_rdy;
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ctrl.io.mem.xsdq_val <> mem.io.mem_xsdq_val;
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ctrl.io.mem.dc_busy := !io.dmem.req_rdy;
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ctrl.io.host.start ^^ io.host.start;
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ctrl.io.imem ^^ io.imem;
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// ctrl.io.console ^^ io.console;
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ctrl.io.wb.waddr <> wb.io.wb_waddr;
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ctrl.io.wb.wen <> wb.io.wb_wen;
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// TODO: SHOULD BE THE FOLLOWING BUT NEED BETTER INTERFACE CHUNKS
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// mem.io.dmem >< io.dmem;
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mem.io.dmem_req_val ^^ io.dmem.req_val;
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mem.io.dmem_req_rdy ^^ io.dmem.req_rdy;
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mem.io.dmem_req_op ^^ io.dmem.req_op;
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mem.io.dmem_req_addr ^^ io.dmem.req_addr;
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mem.io.dmem_req_data ^^ io.dmem.req_data;
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mem.io.dmem_req_wmask ^^ io.dmem.req_wmask;
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mem.io.dmem_req_tag ^^ io.dmem.req_tag;
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mem.io.dpath_rs2 <> dpath.io.dpath.rs2;
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mem.io.dpath_waddr <> dpath.io.dpath.waddr;
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mem.io.dpath_alu_out <> dpath.io.dpath.alu_out;
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wb.io.dmem_resp_val ^^ io.dmem.resp_val;
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wb.io.dmem_resp_data ^^ io.dmem.resp_data;
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wb.io.dmem_resp_tag ^^ io.dmem.resp_tag;
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io.console.bits := dpath.io.dpath.rs1(7,0);
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io.console.valid := ctrl.io.console.valid;
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ctrl.io.console.rdy := io.console.rdy;
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}
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}
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